Encoding of Terms in EMB-Based Mealy FSMs

A method is proposed targeting implementation of FPGA-based Mealy finite state machines. The main goal of the method is a reduction for the number of look-up table (LUT) elements and their levels in FSM logic circuits. To do it, it is necessary to eliminate the direct dependence of input memory functions and FSM output functions on FSM inputs and state variables. The method is based on encoding of the terms corresponding to rows of direct structure tables. In such an approach, only terms depend on FSM inputs and state variables. Other functions depend on variables representing terms. The method belongs to the group of the methods of structural decomposition. The set of terms is divided by classes such that each class corresponds to a single-level LUT-based circuit. An embedded memory block (EMB) generates codes of both classes and terms as elements of these classes. The mutual using LUTs and EMB allows diminishing chip area occupied by FSM circuit (as compared to its LUT-based counterpart). The simple sequential algorithm is proposed for finding the partition of the set of terms by a determined number of classes. The method is based on representation of an FSM by a state transition table. However, it can be used for any known form of FSM specification. The example of synthesis is shown. The efficiency of the proposed method was investigated using a library of standard benchmarks. We compared the proposed with some other known design methods. The investigations show that the proposed method gives better results than other discussed methods. It allows the obtaining of FSM circuits with three levels of logic and regular interconnections.

Implementasi Reduksi Keadaan Rangkaian Digital Sekuensial Metode Bagan Implikasi

The implementation of state reduction in sequential digital circuits is made for learning the topic of state reduction. The method used for state reduction is an implication chart. This method starts with reading the transition table state and transfered into the array structure. Based on this array structure a table or chart of initial implications is arranged. The next process is to change the contents of the table if there are cells that meet the requirements to be declared as identical or not identical. This process is repeated continuously until there is no change in cell contents. The state of reduction implementation is made using the Python programming language and PHP. The results of the implementation are successful for the state transition table with 1 input and 1 output.

System for Identifying and Correcting Invalid Words in the Devanagari Script for Text to Speech Engine

The Text To Speech (TTS) system takes text as an input and generates speech as an output. If input text is incorrect then overall quality of speech output may degrade. The main aim of the proposed system is to provide correct input text to the TTS. The system takes Unicode word as an input, identifies invalid word and corrects it by inserting, deleting or updating characters of the word. In this system, the State Machine is used to identify and correct invalid word in the Devanagari script which in turn is based on rules. Rules are developed for converting character to input symbol. Actions and States are identified for State Machine. Finally, the state transition table is developed for validation and correction of word. Using this system, incorrect words of the Devanagari script can be corrected to valid words (word contains all the valid Devanagari syllables) based on Devanagari script grammar. Since, all Devanagari characters are not present in Hindi language; this system will correct these nonHindi characters to Hindi

System for Identifying and Correcting Invalid Words in the Devanagari Script for Text to Speech Engine

The Text To Speech (TTS) system takes text as an input and generates speech as an output. If input text is incorrect then overall quality of speech output may degrade. The main aim of the proposed system is to provide correct input text to the TTS. The system takes Unicode word as an input, identifies invalid word and corrects it by inserting, deleting or updating characters of the word. In this system, the State Machine is used to identify and correct invalid word in the Devanagari script which in turn is based on rules. Rules are developed for converting character to input symbol. Actions and States are identified for State Machine. Finally, the state transition table is developed for validation and correction of word. Using this system, incorrect words of the Devanagari script can be corrected to valid words (word contains all the valid Devanagari syllables) based on Devanagari script grammar. Since, all Devanagari characters are not present in Hindi language; this system will correct these nonHindi characters to Hindi.

HYPER-MINIMIZATION FOR DETERMINISTIC TREE AUTOMATA

Hyper-minimization is a recent automaton compression technique that can reduce the size of an automaton beyond the limits imposed by classical minimization. The additional compression power is enabled by allowing a finite difference in the represented language. The necessary theory for hyper-minimization is developed for (bottom-up) deterministic tree automata. The hyper-minimization problem for deterministic tree automata is reduced to the hyper-minimization problem for deterministic finite-state string automata, for which fast algorithms exist. The fastest algorithm obtained in this way runs in time [Formula: see text], where m is the size of the transition table and n is the number of states of the input tree automaton.

DESIGN AND OPTIMIZATION OF SINGLE AND MULTIPLE-LOOP REVERSIBLE AND QUANTUM FEEDBACK CIRCUITS

The majority of work in reversible logic circuits has been limited to combinational logic. Researchers are now beginning to suggest designs for sequential circuits. In this paper we propose a new method to design and optimize feedback reversible logic circuits and a specific group of quantum logic circuits based on the reversible state transition table and genetic algorithms (GA). To show the efficiency of the proposed method, some reversible sequential elements such as D and T flip-flops (FFs), with and without clock and reset, and edge triggered FFs are designed. We have also extended our method to multiple loop feedback circuits. The proposed circuits are highly optimized using a GA synthesis tool that allows don't care values. Some of the designs in this paper are presented in other papers; however, the comparisons show that the quantum cost and number of garbage inputs/outputs are reduced efficiently by our method.