Verified tensor-program optimization via high-level scheduling rewrites

We present a lightweight Coq framework for optimizing tensor kernels written in a pure, functional array language. Optimizations rely on user scheduling using series of verified, semantics-preserving rewrites. Unusually for compilation targeting imperative code with arrays and nested loops, all rewrites are source-to-source within a purely functional language. Our language comprises a set of core constructs for expressing high-level computation detail and a set of what we call reshape operators, which can be derived from core constructs but trigger low-level decisions about storage patterns and ordering. We demonstrate that not only is this system capable of deriving the optimizations of existing state-of-the-art languages like Halide and generating comparably performant code, it is also able to schedule a family of useful program transformations beyond what is reachable in Halide.

Production Scheduling of Personalized Fashion Goods in a Mass Customization Environment

The COVID-19 pandemic has put fashion manufacturers’ needs for optimization in the spotlight. This study argues that mass customization is becoming increasingly instrumental for offering consumers individualized solutions and that suppliers of fashion have to look for more sophisticated solutions in order to face the increasing demand for more sustainable products. With the deduction of a mathematical model derived from production sequencing it became evident that sustainability can be associated with a level production schedule and that cost-based production optimization is useful in achieving holistic sustainability in the fashion industry. The flexibility in the conceived mathematical model specifications allows for a generalizable approach, not limited to a single branch of the fashion industry. This paper additionally delivers a cost-based optimization approach which fashion companies, operating in a mass customization production layout, can easily implement without extensive know-how. The proposed two-stage algorithm is based on the concept of level scheduling. In a first stage, the algorithm determines a feasible production sequence in a time-efficient way while, in the second stage, it further advances the efficiency of the solution. Thus, it offers a framework to optimize a production in a mass customization environment and can contribute to a company taking major steps towards a holistic sustainable orientation as available resources are used more (cost) efficiently.

A QMM-MOP methodology for the maintenance scheduling of multistage manufacturing systems with a stream of deterioration

In multistage manufacturing systems, a stream-of-deterioration (SOD) phenomenon poses two challenges for effective preventive-maintenance (PM) scheduling. First, the deterioration of each machine contributes to the deterioration of the final-product quality, and thus timely PM should be conducted to prevent excessive quality deterioration. Second, the deterioration of different machines leads to different degrees of deterioration in the final-product quality; thus, the PM of different machines will result in different degrees of improvement in the final-product quality. To address both challenges, a QMM-MOP methodology that adopts an interactive bi-level scheduling framework is proposed. In machine-level scheduling, a quality-integrated maintenance model (QMM) is developed by incorporating intermediate-product quality deterioration into the total cost to schedule timely PM for each individual machine. In system-level scheduling, maintenance-operation prioritization (MOP), based on a SOD-enabled quality-improvement factor, is proposed to select machines for PM. The case study shows that the proposed methodology can ensure a higher final-product quality with a lower total cost. The contribution of this paper is to develop a QMM-MOP methodology that integrates product-quality improvement into an interactive bi-level PM scheduling framework and enables MOP based on the-quality improvement factor to best improve the final-product quality.

A Review of Prediction and Optimization for Sequence-Driven Scheduling in Job Shop Flexible Manufacturing Systems

This article reviews the state of the art of prediction and optimization for sequence-driven scheduling in job shop flexible manufacturing systems (JS-FMSs). The objectives of the article are to (1) analyze the literature related to algorithms for sequencing and scheduling, considering domain, method, objective, sequence type, and uncertainty; and to (2) examine current challenges and future directions to promote the feasibility and usability of the relevant research. Current challenges are summarized as follows: less consideration of uncertainty factors causes a gap between the reality and the derived schedules; the use of stationary dispatching rules is limited to reflect the dynamics and flexibility; production-level scheduling is restricted to increase responsiveness owing to product-level uncertainty; and optimization is more focused, while prediction is used mostly for verification and validation, although prediction-then-optimization is the standard stream in data analytics. In future research, the degree of uncertainty should be quantified and modeled explicitly; both holistic and granular algorithms should be considered; product sequences should be incorporated; and sequence learning should be applied to implement the prediction-then-optimization stream. This would enable us to derive data-learned prediction and optimization models that output accurate and precise schedules; foresee individual product locations; and respond rapidly to dynamic and frequent changes in JS-FMSs.

A Comparative Study of Block Incomplete Sparse Approximate Inverses Preconditioning on Tesla K20 and V100 GPUs

Incomplete Sparse Approximate Inverses (ISAI) has shown some advantages over sparse triangular solves on GPUs when it is used for the incomplete LU based preconditioner. In this paper, we extend the single GPU method for Block–ISAI to multiple GPUs algorithm by coupling Block–Jacobi preconditioner, and introduce the detailed implementation in the open source numerical package PETSc. In the experiments, two representative cases are performed and a comparative study of Block–ISAI on up to four GPUs are conducted on two major generations of NVIDIA’s GPUs (Tesla K20 and Tesla V100). Block–Jacobi preconditioning with Block–ISAI (BJPB-ISAI) shows an advantage over the level-scheduling based triangular solves from the cuSPARSE library for the cases, and the overhead of setting up Block–ISAI and the total wall clock times of GMRES is greatly reduced using Tesla V100 GPUs compared to Tesla K20 GPUs.

GPU Preconditioning for Block Linear Systems Using Block Incomplete Sparse Approximate Inverses

Solving sparse triangular systems is the building block for incomplete LU- (ILU-) based preconditioning, but parallel algorithms, such as the level-scheduling scheme, are sometimes limited by available parallelism extracted from the sparsity pattern. In this study, the block version of the incomplete sparse approximate inverses (ISAI) algorithm is studied, and the block-ISAI is considered for preconditioning by proposing an efficient algorithm and implementation on graphical processing unit (GPU) accelerators. Performance comparisons are carried out between the proposed algorithm and serial and parallel block triangular solvers from PETSc and cuSPARSE libraries. The experimental results show that GMRES (30) with the proposed block-ISAI preconditioning achieves accelerations 1.4 × –6.9 × speedups over that using the cuSPARSE library on NVIDIA Tesla V100 GPU.

Memory-Aware Scheduling Parallel Real-Time Tasks for Multicore Systems

Shared resources on the multicore chip, such as main memory, are increasingly becoming a point of contention. Traditional real-time task scheduling policies focus on solely on the CPU, and do not take in account memory access and cache effects. In this paper, we propose parallel real-time tasks scheduling (PRTTS) policy on multicore platforms. Each set of tasks is represented as a directed acyclic graph (DAG). The priorities of tasks are assigned according to task periods Rate Monotonic (RM). Each task is composed of three phases. The first phase is read memory stage, the second phase is execution phase and the third phase is write memory phase. The tasks use locks and critical sections to protect data access. The global scheduler maintains the task pool in which tasks are ready to be executed which can run on any core. PRTTS scheduling policy consists of two levels: the first level scheduling schedules ready real-time tasks in the task pool to cores, and the second level scheduling schedules real-time tasks on cores. Tasks can preempt the core on running tasks of low priority. The priorities of tasks which want to access memory are dynamically increased above all tasks that do not access memory. When the data accessed by a task is in the cache, the priority of the task is raised to the highest priority, and the task is scheduled immediately to preempt the core on running the task not accessing memory. After accessing memory, the priority of these tasks is restored to the original priority and these tasks are pended, the preempted task continues to run on the core. This paper analyzes the schedulability of PRTTS scheduling policy. We derive an upper-bound on the worst-case response-time for parallel real-time tasks. A series of extensive simulation experiments have been performed to evaluate the performance of proposed PRTTS scheduling policy. The results of simulation experiment show that PRTTS scheduling policy offers better performance in terms of core utilization and schedulability rate of tasks.