scholarly journals Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

Algorithms ◽  
2021 ◽  
Vol 14 (7) ◽  
pp. 198
Author(s):  
Mário P. Véstias ◽  
Horácio C. Neto
Keyword(s):  
Arithmetic Functions ◽  
Optimized Design ◽  
Decimal Arithmetic ◽  
Binary Arithmetic ◽  
Decimal Adder ◽  
Decimal Fractions ◽  
Decimal Multiplication ◽  
And Performance ◽  
Improve State ◽  
Dedicated Hardware

Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands.

Decimal Hardware Multiplier

2018 ◽  
pp. 4607-4618
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Number System ◽  
Floating Point ◽  
Binary Number ◽  
Correct Result ◽  
Fundamental Operation ◽  
Floating Point Arithmetic ◽  
Decimal Arithmetic ◽  
Decimal Numbers ◽  
Decimal Multiplication ◽  
Point Arithmetic

IEEE-754 2008 has extended the standard with decimal floating point arithmetic. Human-centric applications, like financial and commercial, depend on decimal arithmetic since the results must match exactly those obtained by human calculations without being subject to errors caused by decimal to binary conversions. Decimal Multiplication is a fundamental operation utilized in many algorithms and it is referred in the standard IEEE-754 2008. Decimal multiplication has an inherent difficulty associated with the representation of decimal numbers using a binary number system. Both bit and digit carries, as well as invalid results, must be considered in decimal multiplication in order to produce the correct result. This article focuses on algorithms for hardware implementation of decimal multiplication. Both decimal fixed-point and floating-point multiplication are described, including iterative and parallel solutions.

Decimal Hardware Multiplier

2019 ◽  
pp. 722-736
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Number System ◽  
Floating Point ◽  
Binary Number ◽  
Correct Result ◽  
Fundamental Operation ◽  
Floating Point Arithmetic ◽  
Decimal Arithmetic ◽  
Decimal Numbers ◽  
Decimal Multiplication ◽  
Point Arithmetic

IEEE-754 2008 has extended the standard with decimal floating-point arithmetic. Human-centric applications, like financial and commercial, depend on decimal arithmetic since the results must match exactly those obtained by human calculations without being subject to errors caused by decimal to binary conversions. Decimal multiplication is a fundamental operation utilized in many algorithms, and it is referred in the standard IEEE-754 2008. Decimal multiplication has an inherent difficulty associated with the representation of decimal numbers using a binary number system. Both bit and digit carries, as well as invalid results, must be considered in decimal multiplication in order to produce the correct result. This chapter focuses on algorithms for hardware implementation of decimal multiplication. Both decimal fixed-point and floating-point multiplication are described, including iterative and parallel solutions.

Design of a Compact Crossover Diffuser for Micro Gas Turbines Using a Mean-Line Code

2019 ◽  
Vol 36 (4) ◽  
pp. 347-357
Author(s):  
C.J. Burger ◽  
S.J. van der Spuy ◽  
T.W. von Backström
Keyword(s):  
Gas Turbines ◽  
Optimized Design ◽  
One Dimensional ◽  
Micro Gas Turbine ◽  
Engine Thrust ◽  
Design Variables ◽  
Performance Effects ◽  
Computational Fluid Dynamics Cfd ◽  
And Performance ◽  
Good Agreement

Abstract The design and validation of a Compact Crossover Diffuser (CCD) to replace the size-limited radial diffuser and axial de-swirl cascade of an existing Micro Gas Turbine (MGT) is discussed. A CCD strives to combine the performance of a channel diffuser with the operating range and efficiency of a vaneless diffuser. The development of a one-dimensional Mean-Line Code (MLC) is presented, which aids the designer in preliminary design and performance evaluation of the CCD. Design graphs indicating the performance effects of changing the primary design variables are developed and shown. The MLC is numerically validated using Computational Fluid Dynamics (CFD). Good agreement is seen between the MLC and CFD results, predicting the design point PRss(2-4) to within 1.4 %. A CFD optimized CCD was manufactured and tested. Agreement between the CFD and experimental results for PRts(0-4) is within 7.58 % at 106 kRPM. A numerically predicted increase in PRts(0-4) from 3.31, to 3.53, to 3.83 is seen for the vaneless-, MLC optimized-, and CFD optimized-design respectively. An experimental increase of 82.3 % in engine thrust and 80.0 % in total-to-static pressure recovery across the compressor stage was measured when retrofitting the BMT120KS with a new impeller and CCD.

scholarly journals Design Optimization and Performance Analysis of a Multi-kW Thermoacoustic Electric Generator Using DeltaEC Model

2021 ◽  
pp. 1-19
Author(s):  
Srinath Somu ◽  
Deanna A. Lacoste ◽  
Saumitra Saxena ◽  
William Roberts ◽  
Robert M. Keolian
Keyword(s):  
Heat Source ◽  
Heat Recovery ◽  
Waste Heat Recovery ◽  
Power Plants ◽  
Waste Heat ◽  
Research Work ◽  
Acoustic Power ◽  
Optimized Design ◽  
Electric Generator ◽  
And Performance

Abstract Waste heat recovery from power plants and industries requires a new type of electricity generator and related technological developments. The current research work is aimed at the design of a multi-kilowatt thermoacoustic electric generator, which can be employed as the bottoming cycle of a gas-turbine power plant or for industrial waste heat recovery. The proposed device converts thermal energy into acoustic power and subsequently uses a piezoelectric alternator to convert acoustic power into electricity. The challenge in designing such a device is that it has to be acoustically balanced. The performance of the device is greatly affected by numerous parameters such as frequency of the traveling acoustic wave, heat exchanger parameters, regenerator dimensions, acoustic feedback loop, etc. The proposed device is a lab-scale demonstration targeted to produce few kilowatts of electric power from a 20 kWth heat source. DeltaEC software is used to achieve the acoustically balanced configuration of the device. The DeltaEC model outcomes are used to arrive at the optimized design of the device and its components. The analytical method, the optimized geometrical dimensions of thermoacoustic components, and the minimum required conditions of heat source input are presented in this paper.

scholarly journals Optimized design and Performance Analysis of Three Phase Induction Motor using Maxwell Software

2020 ◽  
Vol 8 (6) ◽  
pp. 4103-4107
Keyword(s):  
Induction Motor ◽  
Magnetic Circuit ◽  
Industrial Applications ◽  
Optimized Design ◽  
Prime Mover ◽  
Centrifugal Pumps ◽  
Textile Mills ◽  
Ac Motors ◽  
Three Phase ◽  
And Performance

Three phase induction motors are ac motors which are widely employed as a prime mover in most of the industrial applications such as centrifugal pumps, conveyers, compressors crushers, and drilling machines, textile mills etc. In this paper the performance of an 2.2kW, 400 V, four pole, three phase induction motor was analyzed using RMxprt. RMxprt uses a combination of analytical and magnetic circuit equations to predict the performance of this three-phase induction motor.

scholarly journals Hardware–Software Co-Design for Decimal Multiplication

Computers ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 17
Author(s):  
Riaz-ul-haque Mian ◽  
Michihiro Shintani ◽  
Michiko Inoue
Keyword(s):  
Large Scale ◽  
Process Analysis ◽  
Evaluation Framework ◽  
Multiplication Process ◽  
Decimal Arithmetic ◽  
Area Overhead ◽  
Software And Hardware ◽  
Decimal Multiplication ◽  
Point Arithmetic ◽  
Area Efficient

Decimal arithmetic using software is slow for very large-scale applications. On the other hand, when hardware is employed, extra area overhead is required. A balanced strategy can overcome both issues. Our proposed methods are compliant with the IEEE 754-2008 standard for decimal floating-point arithmetic and combinations of software and hardware. In our methods, software with some area-efficient decimal component (hardware) is used to design the multiplication process. Analysis in a RISC-V-based integrated co-design evaluation framework reveals that the proposed methods provide several Pareto points for decimal multiplication solutions. The total execution process is sped up by 1.43× to 2.37× compared with a full software solution. In addition, 7–97% less hardware is required compared with an area-efficient full hardware solution.

scholarly journals Modeling Geared Turbofan and Open Rotor Engine Performance for Year-2050 Long-Range and Short-Range Aircraft

2020 ◽  
Vol 142 (4) ◽  
Author(s):  
Francesco S. Mastropierro ◽  
Joshua Sebastiampillai ◽  
Florian Jacob ◽  
Andrew Rolt
Keyword(s):  
Short Range ◽  
Pressure Ratio ◽  
Engine Performance ◽  
Optimized Design ◽  
Fuel Burn ◽  
Medium Range ◽  
Open Rotor ◽  
And Performance ◽  
Year 2000 ◽  
Bypass Ratio

Abstract This paper provides design and performance data for two envisaged year-2050 engines: a geared high bypass turbofan for intercontinental missions and a contra-rotating pusher open rotor targeting short to medium range aircraft. It defines component performance and cycle parameters, general arrangements, sizes, and weights. Reduced thrust requirements reflect expected improvements in engine and airframe technologies. Advanced simulation platforms have been developed to model the engines and details of individual components. The engines are optimized and compared with “baseline” year-2000 turbofans and an anticipated year-2025 open rotor to quantify the relative fuel-burn benefits. A preliminary scaling with year-2050 “reference” engines, highlights tradeoffs between reduced specific fuel consumption (SFC) and increased engine weight and diameter. These parameters are converted into mission fuel burn variations using linear and nonlinear trade factors (NLTF). The final turbofan has an optimized design-point bypass ratio (BPR) of 16.8, and a maximum overall pressure ratio (OPR) of 75.4, for a 31.5% TOC thrust reduction and a 46% mission fuel burn reduction per passenger kilometer compared to the respective “baseline” engine–aircraft combination. The open rotor SFC is 9.5% less than the year-2025 open rotor and 39% less than the year-2000 turbofan, while the TOC thrust increases by 8% versus the 2025 open rotor, due to assumed increase in passenger capacity. Combined with airframe improvements, the final open rotor-powered aircraft has a 59% fuel-burn reduction per passenger kilometer relative to its baseline.

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