scholarly journals Design and Implementation of Reduced Power Energy Efficient Binary Coded Decimal Adder

2019 ◽  
Vol 8 (3) ◽  
pp. 185
Author(s):  
N. Saravanakumar ◽  
K. Sakthi Sudhan ◽  
K. N. Vijeyakumar ◽  
S. Saranya
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Delay Reduction ◽  
Second Stage ◽  
Design And Implementation ◽  
Quartus Ii ◽  
Decimal Adder ◽  
Power Delay Product ◽  
Vhdl Code ◽  
Inherent Advantage

<p>This paper presents a novel architecture for low power energy binary represented decimal addition. The proposed BCD adder uses Binary to Excess Six Converter (BESC) block for constant correction to adjusts binary outputs exceeding 9 to correct decimal values and exploits the inherent advantage of reduced delay and switching, due to elimination of long carry propagation in second stage addition as in conventional design and switching OFF of the BESC block for decimal outputs less than 9. The proposed BESC-BCD adder has been designed using VHDL code and synthesized using Altera Quartus II. Experimental results demonstrates that the proposed decimal adder can lead to significant power savings and delay reduction compared to existing BCD adders which is realised in better power-delay product(PDP) performance. For example the PDP saving of the proposed BESC-BCD adder for a 1 digit and 2 digit addition implementations are 11.6% and 16.05% respectively, compared to the best of the designs used for comparison.</p>

scholarly journals Energy and Area Effective Hardware Design of Lifting Approach Discrete Wavelet Transform

2019 ◽  
Vol 7 (3) ◽  
pp. 197
Author(s):  
Khamees Khalaf Hasan ◽  
Ibrahim Khalil Salih ◽  
Abdumuttalib. A. Hussen
Keyword(s):  
Wavelet Transform ◽  
Discrete Wavelet Transform ◽  
Energy Efficient ◽  
Lifting Scheme ◽  
Building Design ◽  
Discrete Wavelet ◽  
Quartus Ii ◽  
Speed Performance ◽  
Level Building ◽  
Vhdl Code

<span lang="EN-US">This paper presents low power Discrete Wavelet Transform DWT architecture, comprising of forward and inverse multilevel transform for 5/3 lifting scheme LS based wavelet transform filter. This LS filter consists of integer adder units and binary shifter rather than multiplier and divider units as in the convolution based filters; hence it is more adaptable to energy efficient hardware performance. The proposed architecture is described using the VHDL based methodology. This VHDL code has been simulated and synthesized to achieve the gate level building design which can be organized to be effectively developed in hardware environment. The Quartus II 9.1 software synthesis tools were employed to implement 2D-DWT VHDL codes in Altera Development board DE2, with Cyclone II FPGA device. The proposed LS wavelet architectures can be attained by focusing on the physical FPGA devices to considerably decrease the needed hardware expenditure and power consumption of the design. The utilized logic and register elements of the architecture are 127 slices (only 1%) usage from 33216 and the architecture consumes only 0.033 W. Simulations were performed using different sizes of gray scale images that authenticate the proposed design and attain a speed performance appropriate for numerous real-time applications.</span>

Design and Implementation of 8x8 Multiplier using 4-2 Compressor and 5-2 Compressor

2016 ◽  
Vol 5 (3) ◽  
pp. 131 ◽  
Author(s):  
K. Hari Kishore ◽  
K. Akhil ◽  
G. Viswanath ◽  
N. Pavan Kumar
Keyword(s):  
Low Power ◽  
High Speed ◽  
Electronic Device ◽  
Logic Gates ◽  
Partial Product ◽  
Transmission Gate ◽  
Design And Implementation ◽  
Wallace Tree ◽  
Minimum Delay ◽  
Power Delay Product

In this paper, a 8x8 multiplier is realized by using 4-2 and 5-2 compressors. Low-power high speed 4-2 compressors and 5-2 compressors are extensively utilized for numerical realizations. Both the compressors circuits that is the 4-2 compressor circuit and 5-2 compressor circuit internally consist of the logic gates i.e. the XOR and XNOR gates.  4-2 compressor circuit has been designed uses a brand new partial-product reduction format that consecutively reduces the utmost output new style of number needs less variety of MOSFET’s compared to Wallace Tree Multipliers. The 4-2 compressor used is created from high-speed and consists of logic gates XOR and XNOR gates and transmission gate primarily based electronic device. The regular delay and switching energy also called as power-delay product (PDP) is differentiated with the 5-2 compressor enforced with 4-2 Compressors and while not compressors, and is evidenced to own minimum delay and PDP. Simulations are performed by mistreatment Xilinx ten.1 ISE.

scholarly journals Noise measurement in high-speed domino pseudo-CMOS keeper

2018 ◽  
Vol 52 (1-2) ◽  
pp. 20-27
Author(s):  
R Jaikumar ◽  
P Poongodi
Keyword(s):  
Low Power ◽  
High Speed ◽  
Noise Immunity ◽  
Delay Reduction ◽  
Power Dynamic ◽  
Unity Noise Gain ◽  
Power Delay Product ◽  
The Cost ◽  
Domino Circuits ◽  
Or Gate

Noise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The proposed technique is able to achieve reduced delay, power consumption, and better noise immunity by using always ON keeper. The simulation results show that the proposed technique exhibits 41%, 39%, and 19% delay reduction when compared with the low power dynamic circuit for two-input OR gate, two-input EX-OR gate, and 4:1 multiplexer. The proposed logic also performs better as compared to a low power dynamic circuit with 24%, 21%, and 14% reduction in power-delay product for two-input OR gate, two-input EX-OR gate, and four input MUX, respectively. The unity noise gain is also improved as compared to all other existing methods.

scholarly journals Energy and Area Effective Hardware Design of Lifting Approach Discrete Wavelet Transform

2019 ◽  
Vol 7 (3) ◽  
pp. 203
Author(s):  
Khamees Khalaf Hasan ◽  
Ibrahim Khalil Salih ◽  
Abdumuttalib. A. Hussen
Keyword(s):  
Wavelet Transform ◽  
Discrete Wavelet Transform ◽  
Energy Efficient ◽  
Lifting Scheme ◽  
Building Design ◽  
Discrete Wavelet ◽  
Quartus Ii ◽  
Speed Performance ◽  
Level Building ◽  
Vhdl Code

<span lang="EN-US">This paper presents low power Discrete Wavelet Transform DWT architecture, comprising of forward and inverse multilevel transform for 5/3 lifting scheme LS based wavelet transform filter. This LS filter consists of integer adder units and binary shifter rather than multiplier and divider units as in the convolution based filters; hence it is more adaptable to energy efficient hardware performance. The proposed architecture is described using the VHDL based methodology. This VHDL code has been simulated and synthesized to achieve the gate level building design which can be organized to be effectively developed in hardware environment. The Quartus II 9.1 software synthesis tools were employed to implement 2D-DWT VHDL codes in Altera Development board DE2, with Cyclone II FPGA device. The proposed LS wavelet architectures can be attained by focusing on the physical FPGA devices to considerably decrease the needed hardware expenditure and power consumption of the design. The utilized logic and register elements of the architecture are 127 slices (only 1%) usage from 33216 and the architecture consumes only 0.033 W. Simulations were performed using different sizes of gray scale images that authenticate the proposed design and attain a speed performance appropriate for numerous real-time applications.</span>

Detailed Analysis of Ultra Low Power Column Compression WALLACE and DADDA Multiplier in Sub-Threshold Regime

2016 ◽  
pp. 78-123
Author(s):  
Priya Gupta ◽  
Anu Gupta ◽  
Abhijit Asati
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Performance Metrics ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Ultra Low Power ◽  
Ripple Carry Adder ◽  
Power Delay Product ◽  
Threshold Regime

In this chapter, the design and comparative analysis is done in between the most well-known column compression multipliers by Wallace and Dadda in sub-threshold regime. In order to reduce the hardware which ultimately reduces area, power and overall power delay product, an energy efficient basic modules of the multipliers like AND gates, half adders, full adders and partial product generate units have been analyzed for sub-threshold operation. At the last stage ripple carry adder is used in both multipliers. The performance metrics considered for the analysis of the multipliers are: power, delay and PDP. Simulation studies are carried out for 8x8-bit and 16x16-bit input data width. The proposed circuits show energy efficient results with Spectre simulations for the TSMC 180nm CMOS technology at 0.4V supply voltage. The proposed multipliers so implemented outperform its counterparts exhibiting low power consumption and lesser propagation delay as compared to conventional multipliers.

Distributed Entropy Energy-Efficient Clustering algorithm for cluster head selection (DEEEC)

2020 ◽  
Vol 39 (6) ◽  
pp. 8139-8147
Author(s):  
Ranganathan Arun ◽  
Rangaswamy Balamurugan
Keyword(s):  
Energy Efficient ◽  
Clustering Algorithm ◽  
Cluster Head ◽  
Residual Energy ◽  
Energy Utilization ◽  
Sensor Nodes ◽  
Second Stage ◽  
Energy Efficient Clustering ◽  
Two Stages ◽  
Ch Selection

In Wireless Sensor Networks (WSN) the energy of Sensor nodes is not certainly sufficient. In order to optimize the endurance of WSN, it is essential to minimize the utilization of energy. Head of group or Cluster Head (CH) is an eminent method to develop the endurance of WSN that aggregates the WSN with higher energy. CH for intra-cluster and inter-cluster communication becomes dependent. For complete, in WSN, the Energy level of CH extends its life of cluster. While evolving cluster algorithms, the complicated job is to identify the energy utilization amount of heterogeneous WSNs. Based on Chaotic Firefly Algorithm CH (CFACH) selection, the formulated work is named “Novel Distributed Entropy Energy-Efficient Clustering Algorithm”, in short, DEEEC for HWSNs. The formulated DEEEC Algorithm, which is a CH, has two main stages. In the first stage, the identification of temporary CHs along with its entropy value is found using the correlative measure of residual and original energy. Along with this, in the clustering algorithm, the rotating epoch and its entropy value must be predicted automatically by its sensor nodes. In the second stage, if any member in the cluster having larger residual energy, shall modify the temporary CHs in the direction of the deciding set. The target of the nodes with large energy has the probability to be CHs which is determined by the above two stages meant for CH selection. The MATLAB is required to simulate the DEEEC Algorithm. The simulated results of the formulated DEEEC Algorithm produce good results with respect to the energy and increased lifetime when it is correlated with the current traditional clustering protocols being used in the Heterogeneous WSNs.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

scholarly journals Low Power and Energy Efficient Street Light System Using IoT

2021 ◽  
Vol 1084 (1) ◽  
pp. 012120
Author(s):  
M Srinivasan ◽  
P Manojkumar ◽  
A Dheepancharavarthy
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Light System ◽  
Power And Energy

scholarly journals Energy Efficiency in Short and Wide-Area IoT Technologies—A Survey

Technologies ◽  
2021 ◽  
Vol 9 (1) ◽  
pp. 22
Author(s):  
Eljona Zanaj ◽  
Giuseppe Caso ◽  
Luca De Nardis ◽  
Alireza Mohammadpour ◽  
Özgü Alay ◽  
...  
Keyword(s):  
Energy Efficiency ◽  
Internet Of Things ◽  
Low Power ◽  
Energy Efficient ◽  
Wide Area ◽  
Wide Area Networks ◽  
The Internet ◽  
Extensive Review ◽  
Research Directions ◽  
The Internet Of Things

In the last years, the Internet of Things (IoT) has emerged as a key application context in the design and evolution of technologies in the transition toward a 5G ecosystem. More and more IoT technologies have entered the market and represent important enablers in the deployment of networks of interconnected devices. As network and spatial device densities grow, energy efficiency and consumption are becoming an important aspect in analyzing the performance and suitability of different technologies. In this framework, this survey presents an extensive review of IoT technologies, including both Low-Power Short-Area Networks (LPSANs) and Low-Power Wide-Area Networks (LPWANs), from the perspective of energy efficiency and power consumption. Existing consumption models and energy efficiency mechanisms are categorized, analyzed and discussed, in order to highlight the main trends proposed in literature and standards toward achieving energy-efficient IoT networks. Current limitations and open challenges are also discussed, aiming at highlighting new possible research directions.

Sign in / Sign up

Export Citation Format

Share Document