Competitive Role of Impurities on the Electrical Activity of as-grown Σ=13, Σ=25 and Deformed Σ=9 Grain boundaries in p-type Silicon Bi-crystals

ABSTRACTElectrical properties of grain boundaries grown by Czochralski process were studied by microwave phase shift (μW-PS) and electron beam induced current (EBIC), before and after gold diffusion at 700°C. As-grown samples had similar doping levels determined by four-point probe measurements but somewhat different oxygen concentrations, obtained by Fourier transform infrared spectroscopy (FTIR). It is shown that the increase of the grain boundary activity due to Au gathering at this planar defect can be hindered by native impurities (likely oxygen). EBIC and μW-PS techniques gave respectively electron diffusion lengths and lifetime values, both in good agreement. EBIC images on deformed Σ =9 showed that extrinsic dislocations do not activate the grain boundary at 300K.

Gold in Flux-less Bonding: Noble or not Noble

ABSTRACTThis work highlights the solder joints reliability issues emerged during the development of a novel compliant contacting technology. The peculiar process in this technology is a mechanical lifting procedure in which a pulling force is exerted onto 63Sn-37Pb (eutectic) solder joints (realized by a flux-less thermo compression process), releasing metal traces from the substrate, to form free standing vertical structures. Since joints mechanical characteristics are critical for the successful fabrication of contacts, different bonding conditions (inert or forming atmosphere, temperature rates) and surface finishing (electroplated gold and preformed solder) have been tested. SEM and EDX analyses have been performed on failing joints to investigate failure causes and classify defect typologies. A constantly higher failure rate (percent number of failing joints) has been observed on gold finished surfaces. Analyses proved that such unusual rate was due to contamination of gold surface left by additives in the plating bath and to the embrittlement caused by gold diffusion into molten solder. Plating additives contamination reduces the wettability of gold surfaces. Concentration values of 3 wt.% for gold, considered safe for surface mount applications, caused embrittlement in solder bumps of 20-40 μm diameters.

Rugged ICs against Corrosion, Shock plus Hotter Temperatures

More applications need microcontrollers to operate at higher temperatures. ICs must survive faster corrosion rate and higher stresses. Improving wire bonding, mold compound or package design requires engineering effort, long evaluation and cost. Because packages are already optimized, further optimization often does not yield the needed improvements. Without changing either chip design or the packaging, one can achieve high temperature reliability by protecting ICs with a gold, over passivation metal (OPM). Low cost CMOS liquid crystal display driver ICs are plated with gold bumps at high volume. Similar gold plating process can be quickly and cheaply implemented over all microcontrollers. Between ICs to the electroplated gold OPM is a barrier metal that slows gold diffusion into aluminum and thereby increases operating life before Au-Al intermetallic wire bond failure. Reliability is improved 6x to 94x under different test conditions. Ball bonding to gold pads are 10% to 40% stronger than onto aluminum pads. Furthermore, gold-gold mono-metallic bonds are ductile and can withstand stresses of extreme package reliability tests consisting of: AATC, MSL1 preconditioning, autoclave and then 190C HTB for 1000 hours. Ductile bonds can strain under mechanical stress and shock. Gold is resistant against corrosion such that packaged ICs survive reliability tests causing mold compound delamination and then moisture ingress from autoclave.