Influence of Modifications Related to Safe Operating Area Demands on Operation of a Specialized Medium/High-Voltage Unity-Gain Buffer

This paper presents safety-related modifications to the improved high-voltage unity-gain buffer and their impact on the operation quality of this circuit. The analyzed buffer architecture combines the virtues of source and gate followers. It provides high input impedance to the gate follower and voltage gain precision to the source follower while retaining a very simple structure and an extremely short signal path. These properties enable its various applications, e.g., as an interconnection of voltage and current mode function blocks in signal paths of medium- and high-voltage integrated circuits. The scrutinized buffer consists of MOS devices with different maximum interterminal voltages, which results in the necessity of enhancing its architecture with a set of safety devices to ensure non-destructive power-up, normal operation, and power-down phases of the buffer operation. The consequences of the implemented safety changes vs. the influence of the physical implementation process on the buffer operation capabilities are presented in comparison to its ancestral source and gate followers. The results show that the analyzed buffer retains the best signal processing quality among the compared buffer structures after the complete physical implementation process.

High Frequency Unity Gain Buffer in 90-nm CMOS Technology

A new unity gain buffer architecture is presented for on-chip CMOS mixed signal applications. The proposed two-stage common source active load (CSAL) buffer with source feedback offers improved performance compared to previously published source follower and source-coupled differential-pair-based unity gain buffers. A 90-nm CMOS design ([Formula: see text] equals 1.2[Formula: see text]V) of the buffer has the following performance parameters. With [Formula: see text]/[Formula: see text] of 10 fF/250 fF, [Formula: see text] is 4.4[Formula: see text]GHz, low frequency gain is 0.16[Formula: see text]dB, maximum input range within 2% gain variation is 260[Formula: see text]mV, total harmonic distortion (THD) is [Formula: see text]63.3[Formula: see text]dB, offset error (input offset minus output offset) is 26[Formula: see text]mV, and 1.06[Formula: see text]mW power consumption. The active load, low gain amplifiers eliminate stability issues and any need for compensation capacitors. The architecture facilitates a relatively large input/output voltage swing while keeping transistors operating in the saturation region, making it suitable for submicron technologies with low rail voltages.