High Frequency Unity Gain Buffer in 90-nm CMOS Technology

2016 ◽  
Vol 25 (07) ◽  
pp. 1650071
Author(s):  
Shuo Li ◽  
Xiaomeng Zhang ◽  
Saiyu Ren
Keyword(s):  
Harmonic Distortion ◽  
Low Frequency ◽  
Cmos Technology ◽  
Common Source ◽  
Active Load ◽  
Cmos Design ◽  
Saturation Region ◽  
Unity Gain ◽  
Unity Gain Buffer ◽  
Voltage Swing

A new unity gain buffer architecture is presented for on-chip CMOS mixed signal applications. The proposed two-stage common source active load (CSAL) buffer with source feedback offers improved performance compared to previously published source follower and source-coupled differential-pair-based unity gain buffers. A 90-nm CMOS design ([Formula: see text] equals 1.2[Formula: see text]V) of the buffer has the following performance parameters. With [Formula: see text]/[Formula: see text] of 10 fF/250 fF, [Formula: see text] is 4.4[Formula: see text]GHz, low frequency gain is 0.16[Formula: see text]dB, maximum input range within 2% gain variation is 260[Formula: see text]mV, total harmonic distortion (THD) is [Formula: see text]63.3[Formula: see text]dB, offset error (input offset minus output offset) is 26[Formula: see text]mV, and 1.06[Formula: see text]mW power consumption. The active load, low gain amplifiers eliminate stability issues and any need for compensation capacitors. The architecture facilitates a relatively large input/output voltage swing while keeping transistors operating in the saturation region, making it suitable for submicron technologies with low rail voltages.

A SIMPLE 1.5 V RAIL-TO-RAIL CMOS CURRENT CONVEYOR

2007 ◽  
Vol 16 (04) ◽  
pp. 627-639 ◽  
Author(s):  
VARAKORN KASEMSUWAN ◽  
WEERACHAI NAKHLO
Keyword(s):  
Power Dissipation ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Current Conveyor ◽  
Common Source ◽  
Output Stage ◽  
Circuit Performance ◽  
Rail To Rail ◽  
Source Follower ◽  
Transfer Error

A simple 1.5 V rail-to-rail CMOS current conveyor is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and HSPICE is used to verify the circuit performance. The current conveyor exhibits low impedance at terminal X (7.2 Ω) and can drive ± 0.6 V to the 300 Ω with the total harmonic distortion of 0.55% at the operating frequency of 3 MHz. The voltage transfer error (between the Y and X terminals) and current transfer error (between the X and Y terminals) are small (-0.2 dB). The power dissipation and bandwidth are 532 μW and over 300 MHz, respectively.

scholarly journals A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces

Sensors ◽  
2020 ◽  
Vol 20 (11) ◽  
pp. 3303
Author(s):  
Jacek Jakusz ◽  
Waldemar Jendernalik ◽  
Grzegorz Blakiewicz ◽  
Miron Kłosowski ◽  
Stanisław Szczepański
Keyword(s):  
Harmonic Distortion ◽  
Low Frequency ◽  
Cmos Technology ◽  
Channel Length ◽  
Temperature Drift ◽  
Nanometer Cmos ◽  
Rail To Rail ◽  
Transconductance Amplifier ◽  
Current Converter ◽  
Linearity Error

The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-Vpp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-Vpp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.

Analysis and Design of a Precise Voltage Buffer

2015 ◽  
Vol 24 (04) ◽  
pp. 1550058 ◽  
Author(s):  
Tohid Moradi Khaneshan ◽  
Mojde Nematzade ◽  
Khayrollah Hadidi ◽  
Abdollah Khoei
Keyword(s):  
Power Supply ◽  
Volterra Series ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Open Loop ◽  
Analysis And Design ◽  
Source Follower ◽  
Unity Gain ◽  
Local Feedback ◽  
Poles And Zeros

An open loop voltage buffer with an exact unity gain using a positive local feedback technique with a conventional source follower is proposed. Stability of the buffer is determined by evaluating the location of the poles and zeros and its linearity is studied using Volterra series expansion. The proposed buffer is laid out in 0.35-μm standard CMOS technology. Post layout simulations demonstrate that the buffer gain is close to unity with less than 0.2% error. The power consumption is 10 mw from a 3.3 V power supply and the achieved total harmonic distortion is -78 dB for a 10 MHz input frequency. Also Monte-Carlo simulations are carried out to investigate effects of random mismatches on the circuit operation.

Compact Design of High-Speed Low-Error Four-Quadrant Current Multiplier with Reduced Power Dissipation

2019 ◽  
Vol 29 (03) ◽  
pp. 2050038
Author(s):  
Mohammad Moradinezhad Maryan ◽  
Seyed Javad Azhari ◽  
Mehdi Ayat ◽  
Reza Rezaei Siahrood
Keyword(s):  
High Speed ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Monte Carlo Analysis ◽  
Saturation Region ◽  
Static Power ◽  
Linearity Error ◽  
Simulation Results ◽  
Compact Design ◽  
Four Quadrant

In this paper, a compact low-power, high-speed, low-error four-quadrant analog multiplier is proposed using a new simple current squarer circuit. The new squarer circuit consists of an NMOS transistor, which operates in saturation region, plus a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has the important property of not using bias currents which results in greatly reduced power. The performance of the proposed design (for passive and active realization of the resistors) has been simulated using HSPICE software in 0.18[Formula: see text][Formula: see text]m TSMC (level-49) CMOS technology. Simulation results with [Formula: see text]-V DC supply voltages show (for passive realization) that the maximum linearity error is 0.35%, the [Formula: see text][Formula: see text]dB bandwidth (BW) is 903[Formula: see text]MHz, the total harmonic distortion (THD) is 0.3% (at 1[Formula: see text]MHz), and the maximum and static power consumption are [Formula: see text]W and [Formula: see text]W, respectively. Also, post-layout simulation results are extracted, which give the maximum linearity error as 0.4%, the [Formula: see text][Formula: see text]dB BW as 657[Formula: see text]MHz and the THD as 0.35%, as well. Moreover, Monte Carlo analysis are performed to verify the satisfactory robustness and reliability of the proposed work’s performance.

A Single-To-Differential LNA using Differential Active Inductor for GPS Applications

Frequenz ◽  
2013 ◽  
Vol 67 (1-2) ◽  
Author(s):  
Hojjat Babaei Kia ◽  
Abu Khari A'ain
Keyword(s):  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Active Inductor ◽  
Active Load ◽  
Common Gate ◽  
Noise Amplifier ◽  
On Chip

AbstractThis paper presents the design of a single-ended input, differential output low noise amplifier for GPS applications in 0.18 µm CMOS technology. This Low Noise Amplifier (LNA) is composed of a common source (CS) amplifier adopted with a common gate, common source (CGCS) balun load. Instead of spiral on-chip inductor, a differential active inductor circuit (DAI) is used as an active load of balun and also

A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS

2016 ◽  
Vol 25 (08) ◽  
pp. 1650084 ◽  
Author(s):  
Liang Zhang ◽  
Dengquan Li ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Input Signal ◽  
Sampling Rate ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Common Source ◽  
Digital Converter ◽  
Input Buffer ◽  
Analog To Digital ◽  
Source Follower ◽  
Time Interleaved

This paper presents a 10-GS/s 6-bit track-and-hold amplifier (THA), which is designed for a 16-way time-interleaved successive approximation register (SAR) analog to digital converter (ADC). To extend the bandwidth, a differential source-degenerated common-source amplifier with peaking inductance is adopted as an input buffer. A switched source follower master track-and-hold stage samples the 800-mVPP differential input signal at 10[Formula: see text]GHz. Moreover, the THA cancels the feed-through in hold mode by a clock-controlled transistor. The proposed THA is simulated in 65-nm CMOS technology. It operates with 1.8/1.2-V supply and consumes 84.8[Formula: see text]mW. At a sampling rate of 10[Formula: see text]GS/s, [Formula: see text]41-dB total harmonic distortion (THD) is achieved with input frequencies up to 5[Formula: see text]GHz.

A COMPACT HIGH-SPEED LOW-POWER RAIL-TO-RAIL BUFFER AMPLIFIER FOR STEP-PULSE SIGNALS

2010 ◽  
Vol 19 (06) ◽  
pp. 1181-1197 ◽  
Author(s):  
CHIH-WEN LU ◽  
CHING-MIN HSIAO
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Feedback Loops ◽  
Common Source ◽  
Experimental Prototype ◽  
Rail To Rail ◽  
Buffer Amplifier ◽  
Voltage Swing

A compact high-speed low-power rail-to-rail buffer amplifier, which is suitable for driving heavy capacitive loads, is proposed. The buffer amplifier is composed of a pair of push-pull output transistors with two feedback loops consisting of a pair of complementary error amplifiers and a pair of complementary common-source amplifiers. The buffer draws little current while static but has a large driving capability while transient. A mutual bias scheme is also proposed to reduce the power consumption and the die area for LCD applications. An experimental prototype buffer amplifier implemented in a 0.35 μm CMOS technology demonstrates that the settling time is 1.5 μs for a voltage swing of 0.1 ~ (VDD–0.1) V under a 600 pF capacitance load. Quiescent current of 4 μA is measured. The area of this buffer is 32 × 109 μm2.

scholarly journals Association Between Brain Activation and Functional Connectivity

2018 ◽  
Vol 29 (5) ◽  
pp. 1984-1996 ◽  
Author(s):  
Dardo Tomasi ◽  
Nora D Volkow
Keyword(s):  
Functional Connectivity ◽  
Brain Activity ◽  
Low Frequency ◽  
Brain Activation ◽  
Blood Oxygen Level Dependent ◽  
Common Source ◽  
Functional Connectivity Density ◽  
Density Mapping ◽  
Human Connectome Project ◽  
Bold Responses

Abstract The origin of the “resting-state” brain activity recorded with functional magnetic resonance imaging (fMRI) is still uncertain. Here we provide evidence for the neurovascular origins of the amplitude of the low-frequency fluctuations (ALFF) and the local functional connectivity density (lFCD) by comparing them with task-induced blood-oxygen level dependent (BOLD) responses, which are considered a proxy for neuronal activation. Using fMRI data for 2 different tasks (Relational and Social) collected by the Human Connectome Project in 426 healthy adults, we show that ALFF and lFCD have linear associations with the BOLD response. This association was significantly attenuated by a novel task signal regression (TSR) procedure, indicating that task performance enhances lFCD and ALFF in activated regions. We also show that lFCD predicts BOLD activation patterns, as was recently shown for other functional connectivity metrics, which corroborates that resting functional connectivity architecture impacts brain activation responses. Thus, our findings indicate a common source for BOLD responses, ALFF and lFCD, which is consistent with the neurovascular origin of local hemodynamic synchrony presumably reflecting coordinated fluctuations in neuronal activity. This study also supports the development of task-evoked functional connectivity density mapping.

A 12-BIT 400-MS/s CURRENT-STEERING DAC WITH DEGLITCHING TECHNIQUE

2014 ◽  
Vol 23 (01) ◽  
pp. 1450004 ◽  
Author(s):  
XIAOBO XUE ◽  
XIAOLEI ZHU ◽  
QIFENG SHI ◽  
LENIAN HE
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Measurement Results ◽  
Voltage Swing ◽  
Current Steering Dac ◽  
Low Supply Voltage

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch–driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch–driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than ±0.6 LSB.

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