ternary decision diagram
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Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Tulasi Naga Jyothi Kolanti ◽  
Vasundhara Patel K.S.

Purpose The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors. Design/methodology/approach Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs. Findings The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased. Originality/value The proposed half subtractor and full subtractor show better performance over the existing subtractors.


Author(s):  
Y-Y Yu ◽  
B. W. Johnson

Ternary decision diagram (TDD) is introduced as a new modelling technique to conduct system safety modelling and assessment. In this paper complex systems are broken down to functional modules in order to facilitate the combinatorial modelling process. Quantitatively to assess safety, two failure states are modelled. Three cases of module construction techniques using TDD are discussed. An algorithm is developed for the TDD modular approach, and an example system is exercised to verify the algorithm.


VLSI Design ◽  
2002 ◽  
Vol 14 (3) ◽  
pp. 259-271 ◽  
Author(s):  
Chip-Hong Chang ◽  
Bogdan J. Falkowski

In this article, we have shown, by means of the EXOR Ternary Decision Diagram that the number of literals and product terms of the Fixed Polarity Reed–Muller (FPRM) expansions can be used to fully classify all Boolean functions in NP equivalent class and NPN equivalent class, respectively. Efficient graph based algorithms to compute the complete weight vectors have been presented. The proof and computation method has led to the derivation of a set of characteristic signatures that has low probability of aliasing when used as the Boolean matching filters in library mapping.


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