2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

High performance 40 nm vertical MOSFET within a conventional CMOS process flow

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) ◽

10.1109/vlsit.2001.934944 ◽

2002 ◽

Cited By ~ 2

Author(s):

E. Josse ◽

T. Skotnicki ◽

M. Jurczak ◽

M. Paoli ◽

B. Tormen ◽

...

Keyword(s):

High Performance ◽

Cmos Process ◽

Process Flow

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A 0.13-μm SOI CMOS technology for low-power digital and RF applications

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) ◽

10.1109/vlsit.2001.934959 ◽

2002 ◽

Cited By ~ 14

Author(s):

N. Zamdmer ◽

A. Ray ◽

J.-O. Plouchart ◽

L. Wagner ◽

N. Fong ◽

...

Keyword(s):

Low Power ◽

Cmos Technology ◽

Rf Applications ◽

Soi Cmos

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Highly scalable sub-10F/sup 2/ 1T1C COB cell for high density FRAM

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) ◽

10.1109/vlsit.2001.934974 ◽

2002 ◽

Author(s):

S.Y. Lee ◽

H.H. Kim ◽

D.J. Jung ◽

Y.J. Song ◽

N.W. Jang ◽

...

Keyword(s):

High Density

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Electrical characteristics of TaSi/sub x/N/sub y/ gate electrodes for dual gate Si-CMOS devices

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) ◽

10.1109/vlsit.2001.934940 ◽

2002 ◽

Cited By ~ 1

Author(s):

You-Seok Suh ◽

G. Heuss ◽

Huicai Zhong ◽

Shin-Nam Hong ◽

V. Misra

Keyword(s):

Electrical Characteristics ◽

Gate Electrodes ◽

Dual Gate

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W/WN/poly gate implementation for sub-130 nm vertical cell DRAM

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) ◽

10.1109/vlsit.2001.934932 ◽

2002 ◽

Cited By ~ 2

Author(s):

R. Malik ◽

L. Clevenger ◽

I. McStay ◽

O. Gluschenkov ◽

W. Robl ◽

...

Keyword(s):

Vertical Cell

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Non-uniform chip-temperature dependent signal integrity

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) ◽

10.1109/vlsit.2001.934991 ◽

2002 ◽

Cited By ~ 3

Author(s):

A.H. Ajami ◽

K. Banerjee ◽

M. Pedram

Keyword(s):

Signal Integrity ◽

Temperature Dependent ◽

Chip Temperature ◽

Dependent Signal

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Investigations of bulk dynamic threshold-voltage MOSFET with 65 GHz "normal-mode" f/sub t/ and 220 GHz "over-drive mode" f/sub t/ for RF applications

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) ◽

10.1109/vlsit.2001.934961 ◽

2002 ◽

Author(s):

Chun-Yen Chang ◽

Jiong-Guang Su ◽

Heng-Ming Hsu ◽

Shyh-Chyi Wong ◽

Tiao-Yuan Huang ◽

...

Keyword(s):

Normal Mode ◽

Threshold Voltage ◽

Dynamic Threshold ◽

Drive Mode ◽

Rf Applications

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Oxidation-resistant amorphous TaN barrier for MIM-Ta/sub 2/O/sub 5/ capacitors in giga-bit DRAMs

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) ◽

10.1109/vlsit.2001.934936 ◽

2002 ◽

Cited By ~ 4

Author(s):

Y. Nakamura ◽

I. Asano ◽

M. Hiratani ◽

T. Saito ◽

H. Goto

Keyword(s):

Oxidation Resistant

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Metal gate work function adjustment for future CMOS technology

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) ◽

10.1109/vlsit.2001.934939 ◽

2002 ◽

Cited By ~ 1

Author(s):

Qiang Lu ◽

R. Lin ◽

P. Ranade ◽

Tsu-Jae King ◽

Chenming Hu

Keyword(s):

Work Function ◽

Cmos Technology ◽

Metal Gate ◽

Gate Work Function

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A high performance 100 nm generation SOC technology (CMOS IV) for high density embedded memory and mixed signal LSIs

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) ◽

10.1109/vlsit.2001.934922 ◽

2002 ◽

Cited By ~ 11

Author(s):

K. Miyashita ◽

T. Nakayama ◽

A. Oishi ◽

R. Hasumi ◽

M. Owada ◽

...

Keyword(s):

High Performance ◽

High Density ◽

Embedded Memory ◽

Mixed Signal

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2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

High performance 40 nm vertical MOSFET within a conventional CMOS process flow

A 0.13-μm SOI CMOS technology for low-power digital and RF applications

Highly scalable sub-10F/sup 2/ 1T1C COB cell for high density FRAM

Electrical characteristics of TaSi/sub x/N/sub y/ gate electrodes for dual gate Si-CMOS devices

W/WN/poly gate implementation for sub-130 nm vertical cell DRAM

Non-uniform chip-temperature dependent signal integrity

Investigations of bulk dynamic threshold-voltage MOSFET with 65 GHz "normal-mode" f/sub t/ and 220 GHz "over-drive mode" f/sub t/ for RF applications

Oxidation-resistant amorphous TaN barrier for MIM-Ta/sub 2/O/sub 5/ capacitors in giga-bit DRAMs

Metal gate work function adjustment for future CMOS technology

A high performance 100 nm generation SOC technology (CMOS IV) for high density embedded memory and mixed signal LSIs

Export Citation Format

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

High performance 40 nm vertical MOSFET within a conventional CMOS process flow

A 0.13-μm SOI CMOS technology for low-power digital and RF applications

Highly scalable sub-10F/sup 2/ 1T1C COB cell for high density FRAM

Electrical characteristics of TaSi/sub x/N/sub y/ gate electrodes for dual gate Si-CMOS devices

W/WN/poly gate implementation for sub-130 nm vertical cell DRAM

Non-uniform chip-temperature dependent signal integrity

Investigations of bulk dynamic threshold-voltage MOSFET with 65 GHz "normal-mode" f/sub t/ and 220 GHz "over-drive mode" f/sub t/ for RF applications

Oxidation-resistant amorphous TaN barrier for MIM-Ta/sub 2/O/sub 5/ capacitors in giga-bit DRAMs

Metal gate work function adjustment for future CMOS technology

A high performance 100 nm generation SOC technology (CMOS IV) for high density embedded memory and mixed signal LSIs

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)
Latest Publications