High performance 40 nm vertical MOSFET within a conventional CMOS process flow

2002 ◽  
Author(s):  
E. Josse ◽  
T. Skotnicki ◽  
M. Jurczak ◽  
M. Paoli ◽  
B. Tormen ◽  
...  
Keyword(s):  
High Performance ◽  
Cmos Process ◽  
Process Flow

scholarly journals A Novel Fast-Locking ADPLL Based on Bisection Method

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1382
Author(s):  
Xiaoying Deng ◽  
Huazhang Li ◽  
Mingcheng Zhu
Keyword(s):  
High Performance ◽  
Tuning Range ◽  
Frequency Control ◽  
Control Word ◽  
Cmos Process ◽  
Bisection Method ◽  
Reference Frequency ◽  
Wide Tuning Range ◽  
Cascade Structure ◽  
And Control

Based on the idea of bisection method, a new structure of All-Digital Phased-Locked Loop (ADPLL) with fast-locking is proposed. The structure and locking method are different from the traditional ADPLLs. The Control Circuit consists of frequency compare module, mode-adjust module and control module, which is responsible for adjusting the frequency control word of digital-controlled-oscillator (DCO) by Bisection method according to the result of the frequency compare between reference clock and restructure clock. With a high frequency cascade structure, the DCO achieves wide tuning range and high resolution. The proposed ADPLL was designed in SMIC 180 nm CMOS process. The measured results show a lock range of 640-to-1920 MHz with a 40 MHz reference frequency. The ADPLL core occupies 0.04 mm2, and the power consumption is 29.48 mW, with a 1.8 V supply. The longest locking time is 23 reference cycles, 575 ns, at 1.92 GHz. When the ADPLL operates at 1.28 GHz–1.6 GHz, the locking time is the shortest, only 9 reference cycles, 225 ns. Compared with the recent high-performance ADPLLs, our design shows advantages of small area, short locking time, and wide tuning range.

LOW-POWER, PARALLEL INTERFACE WITH CONTINUOUS-TIME ADAPTIVE PASSIVE EQUALIZER AND CROSSTALK CANCELLATION

2005 ◽  
Vol 15 (02) ◽  
pp. 459-476
Author(s):  
C. PATRICK YUE ◽  
JAEJIN PARK ◽  
RUIFENG SUN ◽  
L. RICK CARLEY ◽  
FRANK O'MAHONY
Keyword(s):  
Low Power ◽  
Electromagnetic Interference ◽  
Continuous Time ◽  
High Speed ◽  
High Performance ◽  
Process Variations ◽  
Cmos Process ◽  
Power Circuit ◽  
Crosstalk Cancellation ◽  
Circuit Components

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.

Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems

2012 ◽  
Vol 203 ◽  
pp. 469-473
Author(s):  
Ruei Chang Chen ◽  
Shih Fong Lee
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Voltage ◽  
Design Flow ◽  
Total Power ◽  
Cmos Process ◽  
Low Power Circuits ◽  
Class D ◽  
Total Power Consumption ◽  
Power Circuits

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

Flexible silicon nanowires sensor for acetone detection on plastic substrates

2021 ◽  
Author(s):  
Kuibo Lan ◽  
Zhi Wang ◽  
Xiaodong Yang ◽  
Junqing Wei ◽  
Yuxiang Qin ◽  
...  
Keyword(s):  
Silicon Nanowires ◽  
High Performance ◽  
Underlying Mechanism ◽  
Environmental Safety ◽  
Cmos Process ◽  
Plastic Substrates ◽  
Irregular Shapes ◽  
Good Potential ◽  
Mechanical Bending ◽  
Acetone Detection

Abstract Acetone commonly exists in daily life and is harmful to human health, therefore the convenient and sensitive monitoring of acetone is highly desired. In addition, flexible sensors have the advantages of light-weight, conformal attachable to irregular shapes, etc. In this study, we fabricated high performance flexible silicon nanowires (SiNWs) sensor for acetone detection by transferring the monocrystalline Si film and metal-assisted chemical etching method on polyethylene terephthalate (PET). The SiNWs sensor enabled detection of gaseous acetone with a concentration as low as 0.1 parts per million (ppm) at flat and bending states. The flexible SiNWs sensor was compatible with the CMOS process and exhibited good sensitivity, selectivity and repeatability for acetone detection at room temperature. The flexible sensor showed performance improvement under mechanical bending condition and the underlying mechanism was discussed. The results demonstrated the good potential of the flexible SiNWs sensor for the applications of wearable devices in environmental safety, food quality, and healthcare.

scholarly journals Toward High Throughput Core-CBCM CMOS Capacitive Sensors for Life Science Applications: A Novel Current-Mode for High Dynamic Range Circuitry

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3370 ◽  
Author(s):  
Saghi Forouhi ◽  
Rasoul Dehghani ◽  
Ebrahim Ghafar-Zadeh
Keyword(s):  
High Performance ◽  
Life Science ◽  
Dynamic Range ◽  
Current Mode ◽  
Capacitive Sensor ◽  
Oxide Semiconductor ◽  
Capacitance Measurement ◽  
Biological Research ◽  
Cmos Process ◽  
Capacitive Sensors

This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive sensor for life science applications. Charge-based capacitance measurement (CBCM) has significantly attracted the attention of researchers for the design and implementation of high-precision CMOS capacitive biosensors. A conventional core-CBCM capacitive sensor consists of a capacitance-to-voltage converter (CVC), followed by a voltage-to-digital converter. In spite of their high accuracy and low complexity, their input dynamic range (IDR) limits the advantages of core-CBCM capacitive sensors for most biological applications, including cellular monitoring. In this paper, after a brief review of core-CBCM capacitive sensors, we address this challenge by proposing a new current-mode core-CBCM design. In this design, we combine CBCM and current-controlled oscillator (CCO) structures to improve the IDR of the capacitive readout circuit. Using a 0.18 μm CMOS process, we demonstrate and discuss the Cadence simulation results to demonstrate the high performance of the proposed circuitry. Based on these results, the proposed circuit offers an IDR ranging from 873 aF to 70 fF with a resolution of about 10 aF. This CMOS capacitive sensor with such a wide IDR can be employed for monitoring cellular and molecular activities that are suitable for biological research and clinical purposes.

A high performance CMOS process for submicron 16 Mb EPROM

2003 ◽  
Author(s):  
A. Bergemont ◽  
S. Deleonibus ◽  
G. Guegan ◽  
B. Guillaumot ◽  
M. Laurens ◽  
...  
Keyword(s):  
High Performance ◽  
Cmos Process

Optoelectronic CMOS Transistors: Performance Advantages for Sub-7nm ULSI, RF ASIC, Memories, and Power MOSFETs

MRS Advances ◽  
2019 ◽  
Vol 4 (48) ◽  
pp. 2585-2591
Author(s):  
James N. Pan
Keyword(s):  
Low Power ◽  
High Voltage ◽  
Series Resistance ◽  
Access Time ◽  
Cmos Process ◽  
Output Current ◽  
Process Flow ◽  
Power Mosfets ◽  
Cmos Transistors ◽  
Low Power Cmos

AbstractSubstantial increase of output current, and Ion / Ioff ratio for sub-7nm low power CMOS transistors, can be accomplished using a novel optoelectronic technology, which is 100% compatible with existing CMOS process flow. For RF or mixed signal ASICs, adding photonic components may improve the cut-off frequency, and reduce series resistance. Products that utilize power regulating devices, such as power MOSFETs, will benefit from the optoelectronic configuration to achieve much lower Rdson and high voltage at the same time. For semiconductor memories, such as DRAM or FLASH, the photonic technique may reduce the ERASE / WRITE / access time and improve the reliability.

Design of a Fourth-Order Sigma-Delta Modulator for Audio Application

2013 ◽  
Vol 380-384 ◽  
pp. 3580-3583
Author(s):  
Ming Yuan Ren ◽  
Tuo Li ◽  
Chang Chun Dong
Keyword(s):  
High Resolution ◽  
Fourth Order ◽  
High Performance ◽  
Sampling Frequency ◽  
Cmos Process ◽  
Sigma Delta Modulator ◽  
Sigma Delta

Based on requirements on high performance and high resolution of modulators, a fourth-order Sigma-Delta modulator for audio application is developed in this paper. The modulator is designed under the commercial 0.5μm CMOS process and the circuits are given simulations by Spectre. The sampling frequency of sigma-delta modulator is 11.264 MHz, and OSR is 256 within the 22 kHz signal bandwidth. Measure performance shows that Sigma-Delta modulator enables its maximum SNR to achieve 103.5dB, and the accuracy of Sigma-Delta modulator is up to 16 bit.

MEMS Monolithic Integration Technology

2013 ◽  
Vol 562-565 ◽  
pp. 1387-1392
Author(s):  
Zhao Yun Zhang ◽  
Zhi Gui Shi ◽  
Zhen Chuan Yang ◽  
Bo Peng
Keyword(s):  
High Temperature ◽  
Aspect Ratio ◽  
High Aspect Ratio ◽  
High Performance ◽  
Monolithic Integration ◽  
Cmos Process ◽  
Integration Technology ◽  
Integrated Technology ◽  
High Temperature Process

The monolithic integrated technology of MEMS was discussed. First discussed the advantages and difficulties faced by the MEMS monolithic integration technology. Second the features and the process of the mainstream MEMS monolithic integration technology was introduced. And finally put forward a SOI MEMS monolithic integration technology, the technology with no high-temperature process, Post-CMOS integrated solution, compatible with the CMOS process. This technology can achieve high aspect ratio, high-performance micro-inertial devices..

Design of a New Low Power Fully Differential Amplifier with Settling Time Enhancement Characteristics

2015 ◽  
Vol 24 (06) ◽  
pp. 1550078 ◽  
Author(s):  
Seid Jafar Hosseinipouya ◽  
Farhad Dastadast
Keyword(s):  
High Performance ◽  
Settling Time ◽  
Cmos Process ◽  
Output Stage ◽  
Common Mode ◽  
Class Ab ◽  
Fully Differential ◽  
Op Amp ◽  
Transconductance Amplifier ◽  
Adaptive Biasing

High performance of fully differential operational transconductance amplifier is designed and implemented using a 0.18-μm CMOS process. The implemented op-amp uses common mode feedback (CMFB) circuit operating in weak inversion region which does not affect other electrical characteristics due to eliminating common mode (CM) levels automatically leading to improve CM rejection ratio (CMRR) of the amplifier significantly. Moreover, the output stage has class-AB operation so that its current can be made larger due to increasing the output current dynamically using adaptive biasing circuit. Additionally, the AC currents of the active loads have been significantly reduced using negative impedances to increase the gain of the amplifier. The results show the GBW 2.3 MHz, slew rate 2.6 V/μs and 1% settling time 150 ns with a capacitive load of 15 pF. This amplifier dissipates only 6.2 μW from a 1.2 V power supply.

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