Novel low‐power and stable memory cell design using hybrid CMOS and MTJ

2021 ◽  
Author(s):  
Govind Prasad ◽  
Deeksha Sahu ◽  
Bipin Chandra Mandi ◽  
Maifuz Ali
Keyword(s):  
Low Power ◽  
Memory Cell ◽  
Cell Design ◽  
Hybrid Cmos ◽  
Stable Memory

High-speed reduced-leakage SRAM memory cell design techniques for low-power 65nm FD-SOI/SON CMOS technology

2014 ◽  
Vol 45 (7) ◽  
pp. 848-856 ◽  
Author(s):  
Deepon Saha ◽  
Subir Kumar Sarkar
Keyword(s):  
Low Power ◽  
High Speed ◽  
Memory Cell ◽  
Cmos Technology ◽  
Cell Design ◽  
Sram Memory ◽  
Design Techniques

A 16 nm Robust DG-FinFET Based 10T Static Random-Access Memory Cell Design for Ultra-Low Power Memory Design

2017 ◽  
Vol 9 (12) ◽  
pp. 1022-1028
Author(s):  
Hitesh Pahuja ◽  
Mintu Tyagi ◽  
Sudhakar Panday ◽  
Balwinder Singh
Keyword(s):  
Low Power ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Cell Design ◽  
Access Memory ◽  
Ultra Low Power ◽  
Memory Design

Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style

2010 ◽  
Vol 6 (4) ◽  
pp. 503-512 ◽  
Author(s):  
Tooraj Nikoubin ◽  
Mahdieh Grailoo ◽  
Sayyed Hasan Mozafari
Keyword(s):  
Low Power ◽  
High Speed ◽  
Design Methodology ◽  
Cell Design ◽  
Transmission Gate ◽  
Hybrid Cmos

A low power memory cell design for SEU protection against radiation effects

2012 ◽  
Author(s):  
Yuriy Shiyanovskii ◽  
Aravind Rajendran ◽  
Chris Papachristou
Keyword(s):  
Low Power ◽  
Radiation Effects ◽  
Memory Cell ◽  
Cell Design

Lateral phase change random access memory cell design for low power operation

2006 ◽  
Vol 13 (2) ◽  
pp. 169-172 ◽  
Author(s):  
F. Merget ◽  
D. H. Kim ◽  
P. Haring Bolivar ◽  
H. Kurz
Keyword(s):  
Low Power ◽  
Phase Change ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Cell Design ◽  
Access Memory ◽  
Power Operation

scholarly journals Design of Low Power 6T Sram with and without ROFs

2020 ◽  
Vol 8 (6) ◽  
pp. 3531-3536
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Research Work ◽  
Memory Cell ◽  
Cell Design ◽  
Sram Cell ◽  
Important Challenge ◽  
Open Faults ◽  
Static Ram ◽  
The Impact

An aggressive scaling in size and the increasing number of the transistor count are the important challenge of the design of Integrated Circuit (IC). In the same manner interconnection lines and resistive opens also became a major problem in present nanometer technology. The resistive open faults [ROFs] represent degradation [1] in connectivity’s within a circuit’s interconnections because of unavoidable manufacturing failures present in both current and future developing technologies. The resistive open fault [ROF] is an imperfect circuit connection that can be modelled as a defect resistors between two nodes of the circuit. The Resistive open faults [2] not causes the functionality of the circuit instantly. But, it causes the delay faults. In this research proposal, the impact of resistive open faults measured in 6-Transistors (6T) Static RAM memory cell design. The proposed 6T Static RAM memory cell implemented in 45nm technology by using Cadence Virtuoso library. The main goal of this proposed research work is to analise the effect of resistive open faults and how it reduce delay and power of 6T Static RAM cell. The resultant outputs of proposed 6T SRAM cell operation with and without ROFs will be compared.

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