Differential block frequency compensation for low‐power multistage amplifiers

2018 ◽  
Vol 32 (2) ◽  
pp. e2517 ◽  
Author(s):  
Tayebeh Asiyabi ◽  
Jafar Torfifard
Keyword(s):  
Low Power ◽  
Frequency Compensation ◽  
Multistage Amplifiers ◽  
Block Frequency

Design and Simulation of Low-Power Multistage Amplifiers

2011 ◽  
Vol 378-379 ◽  
pp. 655-658
Author(s):  
Ming Yuan Ren
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Frequency Compensation ◽  
Transient Responses ◽  
Gain Bandwidth ◽  
Silicon Area ◽  
Multistage Amplifiers ◽  
Capacitive Load ◽  
The Stability ◽  
Multistage Amplifier

This paper presents a low-power multistage amplifier with a novel capacitor-multiplier frequency compensation (CMFC) technique. The proposed compensation strategy can allow the circuit to occupy less silicon area and to drive large capacitive loads more effectively. Moreover, smaller physical capacitance results in higher gain-bandwidth product (GBW) and improved transient responses. Furthermore, the capacitor multiplier stage (CMS) embedded in CMFC creates a left-half plane (LHP) zero, which boosts the phase margin and enhances the stability of the amplifier. Implemented in a commercial 0.5-μm CMOS technology and driving 500pF capacitive load, a three-stage CMFC amplifier achieves over 120dB gain, 1.699MHz GBW and 1.625V/μS average slew rate, while only dissipating 330μW under 3.3V supply.

Frequency-Compensated Bulk-Driven TIA Suitable for Low-Voltage Low-Power Applications

2020 ◽  
pp. 2150121
Author(s):  
Urvashi Bansal ◽  
Maneesha Gupta ◽  
Niranjan Raj
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Transimpedance Amplifier ◽  
Frequency Compensation ◽  
Suitable Alternative ◽  
Small Signal Analysis ◽  
Cmos Design ◽  
Spiral Inductors ◽  
Compensation Technique ◽  
Good Agreement

The importance of a transimpedance amplifier in an optical transceiver is very well known. In this paper, a novel CMOS design of the bulk-driven transimpedance amplifier (BD-TIA) is given where the bridge-shunt peaking-based frequency compensation technique is exploited to improve frequency response. A pre-existing active inductor has been used for the same. The electrical characteristics and functioning of this inductor simulator make it a suitable alternative to both floating and grounded spiral inductors. In order to verify the workability of the proposed circuit, it has been simulated with TSMC CMOS 0.18[Formula: see text][Formula: see text]m process parameters. The proposed circuit is useful in low-voltage low-power VLSI applications as it uses a single supply of 0.75[Formula: see text]V. The power consumption of BD-TIA is very low, being 0.37[Formula: see text]mW, because a standard MOSFET has been replaced by a bulk-driven MOSFET (BDMOS), while the 3-dB bandwidth is observed to be 4.5[Formula: see text]GHz. The mathematical investigation and small signal analysis show that the simulation results are in good agreement.

Impedance Adapting Compensation for Low-Power Multistage Amplifiers

2011 ◽  
Vol 46 (2) ◽  
pp. 445-451 ◽  
Author(s):  
Xiaohong Peng ◽  
Willy Sansen ◽  
Ligang Hou ◽  
Jinhui Wang ◽  
Wuchen Wu
Keyword(s):  
Low Power ◽  
Multistage Amplifiers

ACTIVE-FEEDBACK SINGLE MILLER CAPACITOR FREQUENCY COMPENSATION TECHNIQUES FOR THREE-STAGE AMPLIFIERS

2010 ◽  
Vol 19 (07) ◽  
pp. 1381-1398 ◽  
Author(s):  
MOHAMMAD YAVARI
Keyword(s):  
Low Power ◽  
Small Signal ◽  
Frequency Compensation ◽  
Gain Bandwidth ◽  
Silicon Area ◽  
Active Feedback ◽  
In Series ◽  
Unity Gain ◽  
Simulation Results ◽  
A Current

This paper presents two novel active-feedback single Miller capacitor frequency compensation techniques for low-power three-stage amplifiers. These techniques include the active-feedback single Miller capacitor frequency compensation (AFSMC) and the dual active-feedback single Miller capacitor frequency compensation (DAFSMC). In the proposed techniques, only one Miller capacitor in series with a current buffer is utilized. The main advantages of the proposed three-stage amplifiers are the enhanced unity-gain bandwidth and the reduced silicon area. Small-signal analyses are performed and the design equations are obtained. Extensive HSPICE simulation results are provided to show the usefulness of the proposed AFSMC and DAFSMC amplifiers in both large and small capacitive loads.

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