Frequency-Compensated Bulk-Driven TIA Suitable for Low-Voltage Low-Power Applications

2020 ◽  
pp. 2150121
Author(s):  
Urvashi Bansal ◽  
Maneesha Gupta ◽  
Niranjan Raj
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Transimpedance Amplifier ◽  
Frequency Compensation ◽  
Suitable Alternative ◽  
Small Signal Analysis ◽  
Cmos Design ◽  
Spiral Inductors ◽  
Compensation Technique ◽  
Good Agreement

The importance of a transimpedance amplifier in an optical transceiver is very well known. In this paper, a novel CMOS design of the bulk-driven transimpedance amplifier (BD-TIA) is given where the bridge-shunt peaking-based frequency compensation technique is exploited to improve frequency response. A pre-existing active inductor has been used for the same. The electrical characteristics and functioning of this inductor simulator make it a suitable alternative to both floating and grounded spiral inductors. In order to verify the workability of the proposed circuit, it has been simulated with TSMC CMOS 0.18[Formula: see text][Formula: see text]m process parameters. The proposed circuit is useful in low-voltage low-power VLSI applications as it uses a single supply of 0.75[Formula: see text]V. The power consumption of BD-TIA is very low, being 0.37[Formula: see text]mW, because a standard MOSFET has been replaced by a bulk-driven MOSFET (BDMOS), while the 3-dB bandwidth is observed to be 4.5[Formula: see text]GHz. The mathematical investigation and small signal analysis show that the simulation results are in good agreement.

Stability analysis and compensation technique for low-voltage regulated cascode transimpedance amplifier

2018 ◽  
Vol 71 ◽  
pp. 37-46 ◽  
Author(s):  
Behnam Abdollahi ◽  
Baset Mesgari ◽  
Saeed Saeedi ◽  
Abdolreza Nabavi
Keyword(s):  
Stability Analysis ◽  
Low Voltage ◽  
Transimpedance Amplifier ◽  
Compensation Technique

scholarly journals High-Frequency and Low-Power Output Stages Based on FGMOS Flipped Voltage Follower

2013 ◽  
Vol 2013 ◽  
pp. 1-7 ◽  
Author(s):  
Maneesha Gupta ◽  
Urvashi Singh ◽  
Richa Srivastava
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Performance ◽  
Low Voltage ◽  
Bandwidth Enhancement ◽  
Small Signal Analysis ◽  
Flipped Voltage Follower ◽  
Voltage Follower ◽  
Low Power Dissipation ◽  
Output Stages

Two new high-performance output stages are proposed. These output stages are basically designed by using a flipped voltage follower (FVF). The proposed low-power and low-voltage output stages have utilized the advantages of the FGMOS technology. They are characterized by low-power dissipation, reduced power supply requirement, and larger bandwidth. By using FGMOS-based FVF in place of conventional FVF, the linearity of the output stages has been highly improved. The small-signal analysis of FGMOS-based FVF is done to show the bandwidth enhancement of conventional FVF. The circuits are simulated to demonstrate the effectiveness using SPICE, in TSMC 0.25-micron CMOS device models. The simulation results show that the power supply requirement of the proposed output stages is highly reduced and bandwidths are extremely higher than the conventional circuits.

scholarly journals A Dual Frequency Compensation Technique to Improve Stability and Transient Response for a Three Stage Low-Drop-Out Linear Regulator

2021 ◽  
Vol 8 (2) ◽  
pp. 219-229
Author(s):  
Anass Slamti ◽  
Youness Mehdaoui ◽  
Driss Chenouni ◽  
Zakia Lakhliai
Keyword(s):  
Transient Response ◽  
Low Voltage ◽  
Drop Out ◽  
Frequency Compensation ◽  
Dual Frequency ◽  
Load Current ◽  
Voltage Range ◽  
Dominant Pole ◽  
Compensation Technique ◽  
Ldo Regulator

A novel internal compensation technique named dual frequency compensation is proposed to improve the stability and the transient response of the on-chip output capacitor three stage low-drop-out linear voltage regulator (LDO). It exploits a combination of amplification and differentiation to sufficiently separate the dominant pole from the first non-dominant pole so that the latter is located after the unity gain frequency regardless of the load current value. The proposed LDO regulator is analyzed, designed, and simulated in standard 0.18 µm low voltage CMOS technology. The presented LDO regulator delivers a stable voltage of 1.2 V for an input supply voltage range of 1.35-1.85 V with a maximum line deviation of 4.68mV/V and can supply up to 150mA of the load current. The maximum transient variation of the output voltage is 54.5 mV when the load current pulses from 150mA to 0mA during a fall time of 1µs. The proposed LDO regulator has a low figure of merit compared with recent LDO regulators.

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