K
-band CMOS VCO using a wide tuning range varactor

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

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A Novel Fast-Locking ADPLL Based on Bisection Method

Electronics ◽

10.3390/electronics10121382 ◽

2021 ◽

Vol 10 (12) ◽

pp. 1382

Author(s):

Xiaoying Deng ◽

Huazhang Li ◽

Mingcheng Zhu

Keyword(s):

High Performance ◽

Tuning Range ◽

Frequency Control ◽

Control Word ◽

Cmos Process ◽

Bisection Method ◽

Reference Frequency ◽

Wide Tuning Range ◽

Cascade Structure ◽

And Control

Based on the idea of bisection method, a new structure of All-Digital Phased-Locked Loop (ADPLL) with fast-locking is proposed. The structure and locking method are different from the traditional ADPLLs. The Control Circuit consists of frequency compare module, mode-adjust module and control module, which is responsible for adjusting the frequency control word of digital-controlled-oscillator (DCO) by Bisection method according to the result of the frequency compare between reference clock and restructure clock. With a high frequency cascade structure, the DCO achieves wide tuning range and high resolution. The proposed ADPLL was designed in SMIC 180 nm CMOS process. The measured results show a lock range of 640-to-1920 MHz with a 40 MHz reference frequency. The ADPLL core occupies 0.04 mm2, and the power consumption is 29.48 mW, with a 1.8 V supply. The longest locking time is 23 reference cycles, 575 ns, at 1.92 GHz. When the ADPLL operates at 1.28 GHz–1.6 GHz, the locking time is the shortest, only 9 reference cycles, 225 ns. Compared with the recent high-performance ADPLLs, our design shows advantages of small area, short locking time, and wide tuning range.

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Modelling and analysis of a hybrid CS-CMOS ring VCO with wide tuning range

Microelectronics Journal ◽

10.1016/j.mejo.2020.104752 ◽

2020 ◽

Vol 98 ◽

pp. 104752 ◽

Cited By ~ 1

Author(s):

M. Maiti ◽

A. Majumder ◽

S. Chakrabartty ◽

H. Song ◽

B.K. Bhattacharyya

Keyword(s):

Tuning Range ◽

Wide Tuning Range

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K -band CMOS VCO using a wide tuning range varactor

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A Novel Fast-Locking ADPLL Based on Bisection Method

Modelling and analysis of a hybrid CS-CMOS ring VCO with wide tuning range