Moore's Law and its Effect on Microscopy in the Semiconductor Industry

2008 ◽  
pp. 361-373
Author(s):  
John Mardinly
Keyword(s):  
Semiconductor Industry ◽  
Moore’S Law ◽  
Moore's Law

Moore's Law and the Semiconductor Industry: A Vintage Model*

2005 ◽  
Vol 107 (4) ◽  
pp. 603-630 ◽  
Author(s):  
Ana Aizcorbe ◽  
Samuel Kortum
Keyword(s):  
Semiconductor Industry ◽  
Moore’S Law ◽  
Moore's Law ◽  
Vintage Model

Photolithography Alignment Mark Transfer System for Low Cost, Advanced Packaging, and Bonded Wafer Applications

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001302-001327 ◽  
Author(s):  
Tom Swarbrick ◽  
Keith Best ◽  
Casey Donaher ◽  
Steve Gardner
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Semiconductor Industry ◽  
Final Analysis ◽  
System Throughput ◽  
Latent Image ◽  
Moore’S Law ◽  
Moore's Law ◽  
Advanced Packaging ◽  
Alignment Mark

Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. However, the increase in chip I/O count, driven by Moore's law, and the ability to produce FinFETs below 10nm has presented numerous additional challenges to the existing advanced packaging processes. Furthermore, unlike Moore's law, which predicted the number of transistors in a dense integrated circuit to double approximately every two years, advanced packaging is experiencing an alternate “law”; where instead of the number of transistors increasing, it is the number of functions increasing, within the ever decreasing volume constraints of the final product that drives the technology roadmap. Inevitably, as functionality increases, so does the process complexity and cost. And in the very cost sensitive advanced packaging arena, Outsourced Semiconductor Assembly and Test suppliers (OSATs) need to compensate by reducing their manufacturing costs. This requires the OSAT to reduce material costs, increase throughput, yield, and look for new ways to reduce the number of process steps. One of the ways in which the OSATs have reduced the cost of materials is by removing the silicon wafer from the backend processing altogether; using epoxy mold compound (EMC) to create reconstituted wafers, or by using glass carriers. In the case of glass carriers, it is often the case, where the dice are attached face down on the carrier and subsequent processing prevents the front side patterns from being visible from the top side of the composite stack, even with Infrared (IR) imaging. In this particular case, an additional lithography “clear out” window is defined in photoresist over the alignment mark so the opaque film can be etched away from the alignment mark, the resist is then stripped and cleaned. This additional processing is obviously costly and time consuming. This paper specifically focuses on the concepts, methodology, and performance of a stepper based photolithography solution that utilizes a photoresist latent image to provide temporary alignment marks for the lithography process, removing the need for the additional patterning and etching steps. This revolutionary system employs a backside camera, to align to die through the carrier. A separate exposure unit, calibrated to the alignment camera center, exposes temporary latent image targets which are then detected by the system's regular alignment system during the normal stepper lithography operation. The performance data for the alignment, overlay, and latent image depth control are discussed in detail. The final analysis proves that overlay of < 2um is readily achievable, with no impact on system throughput.

scholarly journals Ultra-precision engineering in lithographic exposure equipment for the semiconductor industry

2012 ◽  
Vol 370 (1973) ◽  
pp. 3950-3972 ◽  
Author(s):  
Robert-H. Munnig Schmidt
Keyword(s):  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Atomic Scale ◽  
Precision Engineering ◽  
Exposure System ◽  
Moore’S Law ◽  
Moore's Law ◽  
Positioning Systems ◽  
Motion System ◽  
The Future

The developments in lithographic tools for the production of an integrated circuit (IC) are ruled by ‘Moore’s Law’: the density of components on an IC doubles in about every two years . The corresponding size reduction of the smallest detail in an IC entails several technological breakthroughs. The wafer scanner, the exposure system that defines those details, is the determining factor in these developments. This review deals with those aspects of the positioning systems inside these wafer scanners that enable the extension of Moore’s Law into the future. The design of these systems is increasingly difficult because of the accuracy levels in the sub-nanometre range coupled with motion velocities of several metres per second. In addition to the use of feedback control for the reduction of errors, high-precision model-based feed-forward control is required with an almost ideally reproducible motion-system behaviour and a strict limitation of random disturbing events. The full mastering of this behaviour even includes material drift on an atomic scale and is decisive for the future success of these machines.

scholarly journals Streamlining Sample Preparation of Semiconductor Materials with a New Site-specific Cleaving Technology

2013 ◽  
Vol 21 (5) ◽  
pp. 22-26
Author(s):  
J. Teshima ◽  
E. Moyal ◽  
Jamil J. Clarke
Keyword(s):  
Sample Preparation ◽  
Lower Cost ◽  
Semiconductor Industry ◽  
Semiconductor Materials ◽  
Consumer Market ◽  
Site Specific ◽  
Moore’S Law ◽  
Packaging Technology ◽  
Moore's Law

The global consumer market wants smaller, faster, more reliable, lower-cost products. The semiconductor industry has responded by the doubling of chip transistor density every two years, closely following Moore's Law. To meet their goals, the industry has made huge investments in R&D and manufacturing to miniaturize components, increase the size of substrates (wafers), improve the productivity of factories, and invent new packaging technology.

PHOTOLITHOGRAPHY ALIGNMENT MARK TRANSFER SYSTEM FOR LOW COST ADVANCED PACKAGING AND BONDED WAFER APPLICATIONS

2016 ◽  
Vol 2016 (1) ◽  
pp. 000315-000320 ◽  
Author(s):  
Keith Best ◽  
Steve Gardner ◽  
Casey Donaher
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Semiconductor Industry ◽  
Final Analysis ◽  
System Throughput ◽  
Latent Image ◽  
Moore’S Law ◽  
Moore's Law ◽  
Advanced Packaging ◽  
Alignment Mark

Abstract Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. However, the increase in chip I/O count, driven by Moore's law, and the ability to produce FinFETs below 10nm have presented numerous additional challenges to the existing advanced packaging processes. Furthermore, unlike Moore's law, which predicted the number of transistors in a dense integrated circuit to double approximately every two years, advanced packaging is experiencing an alternate “law”; where instead of the number of transistors increasing, it is the number of functions increasing, within the ever decreasing volume constraints of the final product that drives the technology roadmap. Inevitably, as functionality increases, so does the process complexity and cost. In this very cost sensitive advanced packaging arena, outsourced semiconductor assembly and test suppliers (OSATs) need to compensate by reducing their manufacturing costs. This requires the OSAT to reduce material costs, increase throughput, yield, and look for new ways to reduce the number of process steps. One of the ways in which the OSATs have reduced the cost of materials is by removing the silicon wafer from back-end processing altogether; using epoxy mold compound (EMC) to create reconstituted wafers, or by using glass carriers. In the case of glass carriers, it is often the case, that the dice are attached face down on the carrier and subsequent processing prevents the front side patterns from being visible from the top side of the composite stack, even with infrared (IR) imaging. In this particular case, an additional lithography “clear out” window is defined in photoresist over the alignment mark so the opaque film can be etched away from the alignment mark, the resist stripped, and the lithography layer reworked. This additional processing is obviously costly and time consuming. This paper specifically focuses on the concepts, methodology, and performance of a stepper-based photolithography solution that utilizes a photoresist latent image to provide temporary alignment marks for the lithography process, removing the need for the additional patterning and etching steps. This revolutionary system employs a backside camera, to align to die through the carrier. A separate exposure unit, calibrated to the alignment camera center, exposes temporary latent image targets which are then detected by the system's regular alignment system during the normal stepper lithography operation. The performance data for the alignment, overlay, and latent image depth control are discussed in detail. The final analysis proves that overlay of < 2μm is readily achievable, with no impact on system throughput.

The innovation curve [Moore's law in semiconductor industry

Computer ◽  
2006 ◽  
Vol 39 (2) ◽  
pp. 8-10 ◽  
Author(s):  
D.A. Grier
Keyword(s):  
Semiconductor Industry ◽  
Moore’S Law ◽  
Moore's Law

Gate Oxides Beyond SiO2

MRS Bulletin ◽  
2008 ◽  
Vol 33 (11) ◽  
pp. 1017-1025 ◽  
Author(s):  
Darrell G. Schlom ◽  
Supratik Guha ◽  
Suman Datta
Keyword(s):  
Power Consumption ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Semiconductor Industry ◽  
San Jose ◽  
Moore’S Law ◽  
Moore's Law ◽  
Computer Performance ◽  
Static Power ◽  
Silicon Based

AbstractThis year marks a major materials milestone in the makeup of silicon-based field-effect transistors: in the microprocessors produced by leading manufacturers, the SiO2 gate dielectric is being replaced by a hafnium-based dielectric. The incredible electronic properties of the SiO2/silicon interface are the reason that silicon has dominated the semiconductor industry and helped it grow to over $250 billion in annual sales, as reported by the Semiconductor Industry Association (SIA), San Jose, CA. The shrinkage of transistor dimensions (Moore's law) has led to tremendous improvements in circuit speed and computer performance. At the same time, however, it has also led to exponential growth in the static power consumption of transistors due to quantum mechanical tunneling through an ever-thinner SiO2 gate dielectric. This has spurred an intensive effort to find an alternative to SiO2 with a higher dielectric constant (K) to temper this exploding power consumption. This article reviews the high-K materials revolution that is enabling Moore's law to continue beyond SiO2.

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