An Extraction Method of SiC Power MOSFET Threshold Voltage

2019 ◽  
pp. 11-20
Author(s):  
W. Jouha ◽  
A. El Oualkadi ◽  
P. Dherbécourt ◽  
E. Joubert ◽  
M. Masmoudi
Keyword(s):  
Threshold Voltage ◽  
Extraction Method ◽  
Power Mosfet

The Effects of Double-Epilayer Structure on Threshold Voltage of Ultralow Voltage Trench Power MOSFET Devices

2007 ◽  
Vol 54 (4) ◽  
pp. 833-839 ◽  
Author(s):  
Qi Wang ◽  
Minhua Li ◽  
Joelle Sharp ◽  
Ashok Challa
Keyword(s):  
Threshold Voltage ◽  
Power Mosfet

scholarly journals Self-Cascode Current-Voltage Curve-Construction Algorithm from Single MOSFET Measurements for Analog Figures-of-Merit Extraction

2019 ◽  
Vol 14 (1) ◽  
pp. 1-6
Author(s):  
Li�gia Martins d'Oliveira ◽  
Valeriya Kilchytska ◽  
Denis Flandre ◽  
Michelly De Souza
Keyword(s):  
Threshold Voltage ◽  
Extraction Method ◽  
New Technologies ◽  
Experimental Measurements ◽  
Saturation Regime ◽  
Figures Of Merit ◽  
Voltage Curve ◽  
Current Voltage ◽  
Current Voltage Curve ◽  
Self Cascode

This paper proposes a curve extraction method for I-V curves and analog figures-of-merit of self-cascode MOSFET associations (SC) using a code that exploits I-V curves of single transistors as input. The method was validated by using experimental measurements of fabricated SC and the very single transistors that compose them. The results indicate a very low error between the SC generated by the code and the measured reference for operation in saturation regime and above threshold voltage, for both the I-V curves and their derivatives. This method is then valid for the assessment of the SC structures in new technologies, avoiding experimental dedicated layouts or complex set-ups.

Silicon Carbide Power MOSFET Model: An Accurate Parameter Extraction Method Based on the Levenberg–Marquardt Algorithm

2018 ◽  
Vol 33 (11) ◽  
pp. 9130-9133 ◽  
Author(s):  
Wadia Jouha ◽  
Ahmed El Oualkadi ◽  
Pascal Dherbecourt ◽  
Eric Joubert ◽  
Mohamed Masmoudi
Keyword(s):  
Silicon Carbide ◽  
Extraction Method ◽  
Parameter Extraction ◽  
Power Mosfet ◽  
Marquardt Algorithm ◽  
Levenberg Marquardt

(Invited) Effect of Threshold-Voltage Instability on SiC Power MOSFET High-Temperature Reliability

2019 ◽  
Vol 41 (8) ◽  
pp. 203-214 ◽  
Author(s):  
Aivars Lelis ◽  
Ronald Green ◽  
Daniel Habersat
Keyword(s):  
High Temperature ◽  
Threshold Voltage ◽  
Power Mosfet ◽  
Voltage Instability

scholarly journals Does the threshold voltage extraction method affect device variability?

2020 ◽  
pp. 1-1
Author(s):  
G. Espineira ◽  
A. J. Garcia-Loureiro ◽  
N. Seoane
Keyword(s):  
Threshold Voltage ◽  
Extraction Method

Power MOSFET Devices and ESD Reliability Evaluations

2012 ◽  
Vol 268-270 ◽  
pp. 1361-1364
Author(s):  
Shen Li Chen ◽  
Wen Ming Lee
Keyword(s):  
Threshold Voltage ◽  
Electron Mobility ◽  
Electrostatic Discharge ◽  
Gate Oxide ◽  
Experimental Results ◽  
Power Mosfet ◽  
Power Mosfets ◽  
Protection Strategy ◽  
Esd Protection ◽  
Protection Circuit

The electrostatic discharge (ESD) reliabilities in different power MOSFETs will be investigated in this paper. From the experimental results, ESD zap pulses at the gate terminal will cause electrons or holes trap in the gate oxide and loss the Si-SiO2 interface integrity, especially for the 100V nDEMOS, 200V nDEMOS, and IRF640, in which they do not have any ESD protection strategy. Electrons or holes trapped in the gate SiO2 layer will be caused the transconductance (Gm) or threshold voltage (Vth) of a MOSFET increasing or reduction, and which is resulted from electron mobility degradation. The RFW2N06RLE and RLD03N06CLE power VDMOS ICs, which with different kinds of ESD protection circuit, are less influenced by ESD pulses experimentally.

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