UML 2.0 State Machines: Complete Formal Semantics Via core state machine

Author(s):  
Harald Fecher ◽  
Jens Schönborn
Author(s):  
Alexander Barkalov ◽  
Larysa Titarenko ◽  
Sławomir Chmielewski

Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSMOptimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.


Author(s):  
Matthew G. McIntire ◽  
Elham Keshavarzi ◽  
Irem Y. Tumer ◽  
Christopher Hoyle

This paper represents a step toward a more complete frame-work of safety analysis early in the design process, specifically during functional modeling. This would be especially useful when designing in a new domain, where many functions have yet to be solved, or for a problem where the functional architecture space is large. In order to effectively analyze the inherent safety of a design only described by its functions and flows, we require some way to simulate it. As an already-available function failure reasoning tool, Function Failure Identification and Propagation (FFIP) utilizes two distinct system models: a behavioral model, and a functional model. The behavioral model simulates system component behavior, and FFIP maps specific component behaviors to functions in the functional model. We have created a new function-failure reasoning method which generalizes failure behavior directly to functions, by which the engineer can create functional models to simulate the functional failure propagations a system may experience early in the design process without a separate behavioral model. We give each basis-defined function-flow element a pre-defined behavior consisting of nominal and failure operational modes, and the resultant effect each mode has on its functions connected flows. Flows are represented by a two-variable object reminiscent of a bond from bond graphs: the state of each flow is represented by an effort variable and a flow-rate variable. The functional model may be thought of as a bond graph where each functional element is a state machine. Users can quickly describe functional models with consistent behavior by constructing their models as Python NetworkX graph objects, so that they may quickly model multiple functional architectures of their proposed system. We are implementing the method in Python to be used in conjunction with other function-failure analysis tools. We also introduce a new method for the inclusion of time in a state machine model, so that dynamic systems may be modeled as fast-evaluating state machines. State machines have no inherent representation of time, while physics-based models simulate along repetitive time steps. We use a more middle-ground pseudo time approach. State transitions may impose a time delay once all of their connected flow conditions are met. Once the entire system model has reached steady state in a timeless sense, the clock is advanced all at once to the first time at which a reported delay is ended. Simulation then resumes in the timeless sense. We seek to demonstrate this modeling method on an electrical power system functional model used in previous FFIP studies, in order to compare the failure scenario results of an exhaustive fault combination experiment with similar results using the FFIP method.


Author(s):  
Messaoudi Nabil ◽  
Allaoua Chaoui ◽  
Mohamed Bettaz

One of the ways to specify dynamic behavior in UML is to model interactions between objects with sequence diagrams, and model the behavior of each object with state machines. In this context, the problem of ensuring consistency between the sequence diagrams and state machines may arise. To verify consistency, the authors propose an approach based on compositions of Büchi automata which allow us to capture the evolution of each object among the lifeline. This paper focuses on UML modeling and verification methods and bridges the gap between theoretical studies on formal semantics and practical studies to implement languages through model transformations. The transformations include basic interactions, state invariants, strict and weak sequencing, and alternative interaction fragments. Ultimately, the results of the transformations are integrated into the Spin model checker as a never claim property. The authors use the Automatic Gate Controller Railway (AGCR) as an example to illustrate their approach.


2015 ◽  
Vol 24 (07) ◽  
pp. 1550101 ◽  
Author(s):  
Raouf Senhadji-Navaro ◽  
Ignacio Garcia-Vargas

This work is focused on the problem of designing efficient reconfigurable multiplexer banks for RAM-based implementations of reconfigurable state machines. We propose a new architecture (called combination-based reconfigurable multiplexer bank, CRMUX) that use multiplexers simpler than that of the state-of-the-art architecture (called variation-based reconfigurable multiplexer bank, VRMUX). The performance (in terms of speed, area and reconfiguration cost) of both architectures is compared. Experimental results from MCNC finite state machine (FSM) benchmarks show that CRMUX is faster and more area-efficient than VRMUX. The reconfiguration cost of both multiplexer banks is studied using a behavioral model of a reconfigurable state machine. The results show that the reconfiguration cost of CRMUX is lower than that of VRMUX in most cases.


2009 ◽  
Vol 250 (1) ◽  
pp. 71-86
Author(s):  
Harald Fecher ◽  
Michael Huth ◽  
Heiko Schmidt ◽  
Jens Schönborn

2014 ◽  
pp. 297-323
Author(s):  
Paolo Arcaini ◽  
Angelo Gargantini ◽  
Elvinia Riccobene ◽  
Patrizia Scandurra

Domain Specific Languages (DSLs) are often defined in terms of metamodels capturing the abstract syntax of the language. For a complete definition of a DSL, both syntactic and semantic aspects of the language have to be specified. Metamodeling environments support syntactic definition issues, but they do not provide any help in defining the semantics of metamodels, which is usually given in natural language. In this chapter, the authors present an approach to formally define the semantics of metamodel-based languages. It is based on a translational technique that hooks to the language metamodel its precise and executable semantics expressed in terms of the Abstract State Machine formal method. The chapter also shows how different techniques can be used for formal analysis of models (i.e., instance of the language metamodel). The authors exemplify the use of their approach on a language for Petri nets.


2018 ◽  
Author(s):  
Dihin Muriyatmoko

Finite state machines have becomeextremely popular over the last decade and helpedgame developers build some pretty fun RTS games[1]. Finite State Machines have been widely used asa tool for developing RTS games, especially aspertains to solving problems related to AI, inputhandling, and game progression [2]. Anyhow, tocontrol game play and user interface for SupplyChain Management (SCM) of Food on RTS gameonly played conventional finite state machine(FSM) design. Therefore in this research isdeveloped Food SCM using Hierarchical StateFinite Machine (HFSM).HFSM allow for a modulardevelopment of states that is more maintainable andscalable[3]. The formalism of HFSM makes thestate machine approach truly applicable to real-lifeembedded systems [4].


1994 ◽  
Vol 31 (4) ◽  
pp. 348-356
Author(s):  
N. R. Poole

An introduction to state machines using a direct implementation philosophy The paper describes a technique for representing state machines that is of value in introducing the concepts of sequential systems. Using a philosophy of implementing each element in a state diagram or algorithmic state machine directly as a circuit entity enables a system to be quickly simulated and verified.


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