Analysis of Cellular Automata and Genetic Algorithm based Test Pattern Generators for Built In Self Test

2012 ◽  
pp. 429-439
Author(s):  
Balwinder Singh ◽  
Sukhleen Bindra Narang ◽  
Arun Khosla
Keyword(s):  
Genetic Algorithm ◽  
Cellular Automata ◽  
Test Pattern ◽  
Self Test ◽  
Built In Self Test ◽  
Pattern Generators

Weighted Cellular Automata Design for Test Pattern Generator Based on Genetic Algorithm

2013 ◽  
Vol 273 ◽  
pp. 840-844 ◽  
Author(s):  
En Min Tan ◽  
Qing Qing Li ◽  
Ji Gang Jiang
Keyword(s):  
Cellular Automata ◽  
Test Pattern ◽  
Pattern Generator ◽  
Fault Coverage ◽  
Test Design ◽  
Design For Test ◽  
Test Length ◽  
Vlsi Test ◽  
Self Test ◽  
Built In Self Test

In built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test length, fault coverage and test consumption, etc. A one-dimension hybrid cellular automata (CA) is used as the core of test pattern generator, with an optimization of its rules based on multi-objectives evolution algorithm. A certain rule which selected from the optimized rule set is adopted to form the weighted cellular automata, by the using of verilog HDL. Experiment results was obtained by simulation of some ISCAS’8n built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test le5 benchmark circuits, and indicated that the test length was reduced obviously (at a ratio above 60%), without losing fault coverage (within a discrepancy of 3%); moreover, the power consumption would be decreased correspondingly.

scholarly journals A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration

2020 ◽  
Vol 9 (12) ◽  
pp. 217-220
Keyword(s):  
Field Programmable Gate Array ◽  
Test Pattern ◽  
Fault Coverage ◽  
Area Overhead ◽  
Field Programmable ◽  
Self Test ◽  
Gate Array ◽  
Built In Self Test ◽  
Pattern Generators ◽  
Logic Blocks

This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.

Sign in / Sign up

Export Citation Format

Share Document