Comparison between quasi-uniform linear cellular automata and linear feedback shift registers as test pattern generators for built-in self-test applications

2003 ◽  
Author(s):  
P.S. Cardoso ◽  
M. Strum ◽  
J.R.de.A. Amazonas ◽  
Wang Jiang Chau
Keyword(s):  
Cellular Automata ◽  
Test Pattern ◽  
Linear Feedback ◽  
Linear Feedback Shift Registers ◽  
Feedback Shift Registers ◽  
Self Test ◽  
Built In Self Test ◽  
Pattern Generators

scholarly journals Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs

VLSI Design ◽  
2000 ◽  
Vol 11 (2) ◽  
pp. 149-159
Author(s):  
Chien-In Henry Chen ◽  
Yingjie Zhou
Keyword(s):  
Test Pattern ◽  
Linear Feedback ◽  
Random Pattern ◽  
Multiple Sequence ◽  
Linear Feedback Shift Registers ◽  
Synthesis Procedure ◽  
Feedback Shift Registers ◽  
Self Test ◽  
Random Patterns ◽  
Test Vectors

Recently a multiple-sequence test generator was presented based on two-dimensional linear feedback shift registers (2-D LFSR). This generator can generate a set of precomputed test vectors obtained by an ATPG tool for detecting random-pattern-resistant faults and particular hard-to-detect faults. In addition, it can generate better random patterns than a conventional LFSR. In this paper we describe an optimized BIST scheme which has a configurable 2-D LFSR structure. Starting from a set of stuck-at faults and a corresponding set of test vectors detecting these faults, the corresponding test pattern generator is determined automatically. A synthesis procedure of designing this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators.

scholarly journals What Causes to Tune a Condition of Exactly Identical Fault-Masks Behaviors in an LFSR based BIST Methodology

2017 ◽  
Vol 10 (04) ◽  
pp. 710-717
Author(s):  
A. Ahmad ◽  
D. Al Abri ◽  
S. S. Al Busaidi ◽  
M. M. Bait-Suwailam
Keyword(s):  
Linear Feedback ◽  
Test Sequence ◽  
Linear Feedback Shift Registers ◽  
Random Test ◽  
Signature Analyzer ◽  
Simulation Results ◽  
Feedback Shift Registers ◽  
Self Test ◽  
Sequence Generator ◽  
Feedback Connections

The authors show that in a Built-In Self-Test (BIST) technique, based on linear-feedback shift registers, when the feedback connections in pseudo-random test-sequence generator and signature analyzer are images of each other and corresponds to primitive characteristic polynomial then behaviors of faults masking remains identical. The simulation results of single stuck-at faults show how the use of such feedback connections in pseudo-random test-sequence generator and signature analyzer yields to mask the same faults.

Weighted Cellular Automata Design for Test Pattern Generator Based on Genetic Algorithm

2013 ◽  
Vol 273 ◽  
pp. 840-844 ◽  
Author(s):  
En Min Tan ◽  
Qing Qing Li ◽  
Ji Gang Jiang
Keyword(s):  
Cellular Automata ◽  
Test Pattern ◽  
Pattern Generator ◽  
Fault Coverage ◽  
Test Design ◽  
Design For Test ◽  
Test Length ◽  
Vlsi Test ◽  
Self Test ◽  
Built In Self Test

In built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test length, fault coverage and test consumption, etc. A one-dimension hybrid cellular automata (CA) is used as the core of test pattern generator, with an optimization of its rules based on multi-objectives evolution algorithm. A certain rule which selected from the optimized rule set is adopted to form the weighted cellular automata, by the using of verilog HDL. Experiment results was obtained by simulation of some ISCAS’8n built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test le5 benchmark circuits, and indicated that the test length was reduced obviously (at a ratio above 60%), without losing fault coverage (within a discrepancy of 3%); moreover, the power consumption would be decreased correspondingly.

scholarly journals A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration

2020 ◽  
Vol 9 (12) ◽  
pp. 217-220
Keyword(s):  
Field Programmable Gate Array ◽  
Test Pattern ◽  
Fault Coverage ◽  
Area Overhead ◽  
Field Programmable ◽  
Self Test ◽  
Gate Array ◽  
Built In Self Test ◽  
Pattern Generators ◽  
Logic Blocks

This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.

Sign in / Sign up

Export Citation Format

Share Document