Effect of MT and VT CMOS, on Transmission Gate Logic for Low Power 4:1 MUX in 45 nm Technology

2012 ◽  
pp. 139-150
Author(s):  
Meenakshi Mishra ◽  
Shyam Akashe ◽  
Shyam Babu
Keyword(s):  
Low Power ◽  
Transmission Gate

Design of Low Power and High Speed 4-Bit Comparator Using Transmission Gate

2013 ◽  
Author(s):  
Govind Prajpat ◽  
Akhilesh Joshi ◽  
Aman Jain ◽  
Kumkum Verma ◽  
Sanjay Kr. Jaiswal
Keyword(s):  
Low Power ◽  
High Speed ◽  
Transmission Gate

Transmission gate‐based 9T SRAM cell for variation resilient low power and reliable internet of things applications

2019 ◽  
Vol 13 (5) ◽  
pp. 584-595 ◽  
Author(s):  
Soumitra Pal ◽  
Vivek Gupta ◽  
Wing Hung Ki ◽  
Aminul Islam
Keyword(s):  
Internet Of Things ◽  
Low Power ◽  
Transmission Gate ◽  
Sram Cell

Low Power Structural Design of 2–4 and 4–16 Line Decoder Logic Circuit

2020 ◽  
Vol 17 (5) ◽  
pp. 2266-2272
Author(s):  
Nikita Kar Chowdhury ◽  
R. Dhanabal ◽  
V. N. Ramakrishnan
Keyword(s):  
Low Power ◽  
Structural Design ◽  
Logic Circuit ◽  
Digital Logic ◽  
Transmission Gate

An analysis of low power 2–4 decoder and 4–16 decoders are made and comparing it with the proposed decoders. The decoder logic circuit have been made utilizing Dual Value Logic (DVL) and Transmission gate logic to actualize a fourteen transistors 2–4 decoder for limiting the transistor count. By utilizing 2–4 pre-decoders and post-decoders to execute 4–16 decoder. Blended digital logic is additionally utilized for this reason. In correlation we have execute a solitary 2–4 decoder with least transistor check and low power utilization which is utilized to structure a 4–16 decoder. CADENCE Virtuoso simulation at 90 nm technology is used and calculated the power and area. We thus made a tabular comparison of our results with the results from previous researches.

scholarly journals A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

2014 ◽  
Vol 2014 ◽  
pp. 1-14 ◽  
Author(s):  
Kunwar Singh ◽  
Satish Chandra Tiwari ◽  
Maneesha Gupta
Keyword(s):  
Low Power ◽  
Transient Response ◽  
High Performance ◽  
Cmos Technology ◽  
Flip Flop ◽  
Parasitic Extraction ◽  
Transmission Gate ◽  
Modern Process ◽  
Capacitive Load ◽  
Area Product

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C2MOS based flip-flop designs mC2MOSff1 and mC2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC2MOSff1. Postlayout simulations indicate that mC2MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes.

scholarly journals Design of Area Efficient, Low-Power and Reliable Transmission Gate-based 10T SRAM Cell for Biomedical Application

2021 ◽  
Author(s):  
Aswini Valluri ◽  
◽  
Sarada Musala ◽  
Muralidharan Jayabalan ◽  
◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Biomedical Application ◽  
Cmos Technology ◽  
Total Power ◽  
Silicon Area ◽  
Transmission Gate ◽  
Read Operation ◽  
Sram Cell ◽  
Total Power Consumption

There is an immense necessity of several kilo bytes of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs (Static Random Access Memory) dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. It commences the read operation directly with the help of Transmission gates with which the data stored in the storage nodes can be read, instead of using the precharge and sense amplifier circuits which suits better for the implantable devices. This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45V.

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