Performance in Sub-25-nm Range: Circuit Model, Ternary Logic Gates and ADC/DAC

Implementation of Unbalanced Ternary Logic Gates with the Combination of Spintronic Memristor and CMOS

Electronics ◽

10.3390/electronics9040542 ◽

2020 ◽

Vol 9 (4) ◽

pp. 542 ◽

Cited By ~ 1

Author(s):

Haifeng Zhang ◽

Zhaowei Zhang ◽

Mingyu Gao ◽

Li Luo ◽

Shukai Duan ◽

...

Keyword(s):

High Efficiency ◽

Load Capacity ◽

Complementary Metal Oxide Semiconductor ◽

Logic Gates ◽

Logic Circuit ◽

Oxide Semiconductor ◽

Ternary Logic ◽

Logic Operations ◽

Almost All ◽

Logic Functions

A memristor is a nanoscale electronic element that displays a threshold property, non-volatility, and variable conductivity. Its composite circuits are promising for the implementation of intelligence computation, especially for logic operations. In this paper, a flexible logic circuit composed of a spintronic memristor and complementary metal-oxide-semiconductor (CMOS) switches is proposed for the implementation of the basic unbalanced ternary logic gates, including the NAND, NOR, AND, and OR gates. Meanwhile, due to the participation of the memristor and CMOS, the proposed circuit has advantages in terms of non-volatility and load capacity. Furthermore, the input and output of the proposed logic are both constant voltages without signal degradation. All these three merits make the proposed circuit capable of realizing the cascaded logic functions. In order to demonstrate the validity and effectiveness of the entire work, series circuit simulations were carried out. The experimental results indicated that the proposed logic circuit has the potential to realize almost all basic ternary logic gates, and even some more complicated cascaded logic functions with a compact circuit construction, high efficiency, and good robustness.

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A Design Technique of CNTFET-Based Ternary Logic Gates in Verilog-A

ECS Journal of Solid State Science and Technology ◽

10.1149/2.0181904jss ◽

2019 ◽

Vol 8 (4) ◽

pp. M45-M52 ◽

Cited By ~ 4

Author(s):

R. Marani ◽

A. G. Perri

Keyword(s):

Logic Gates ◽

Design Technique ◽

Ternary Logic

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Performing Balanced Ternary Logic and Arithmetic Operations with Spiking Neural P Systems with Anti-Spikes

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.505.378 ◽

2012 ◽

Vol 505 ◽

pp. 378-385 ◽

Cited By ~ 2

Author(s):

Xian Wu Peng ◽

Xiao Ping Fan ◽

Jian Xun Liu

Keyword(s):

Logic Gates ◽

P Systems ◽

P System ◽

Ternary Logic ◽

Arithmetic Operations ◽

Spiking Neural P Systems ◽

Addition And Subtraction ◽

Distributed And Parallel Computing ◽

Computing Models ◽

Natural Way

Spiking neural P systems are a class of distributed and parallel computing models inspired by P systems and spiking neural networks.Spiking neural P system with anti-spikes can encode the balanced ternary three digits in a natural way using three states called anti-spikes, no-input and spikes. In this paper we use this variant of SN P system to simulate universal balanced ternary logic gates including AND,OR and NOT gate and to perform some basic balanced ternary arithmetic operations like addition and subtraction on balanced ternary integers. This paper provides an applicational answer to an open problem formulated by L.Pan and Gh. Păun.

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Energy Efficient Tri-State CNFET Ternary Logic Gates

10.20944/preprints201812.0325.v1 ◽

2018 ◽

Cited By ~ 2

Author(s):

Sepher Tabrizchi ◽

Fazel Sharifi ◽

Abdel-Hameed A. Badawy

Keyword(s):

Carbon Nanotube ◽

Field Effect Transistors ◽

Logic Gates ◽

Logic Circuits ◽

Ternary Logic ◽

Large Area ◽

Logic Function ◽

Correct Operation ◽

Power Efficient ◽

Simulation Results

Traditional silicon binary circuits continue to face challenges such as high leakage power dissipation and large area of interconnections. Multiple-Valued Logic (MVL) and nano-devices are two feasible solutions to overcome these problems. In this paper, we present a novel method to design ternary logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs). The proposed designs use the unique properties of CNFETs, e.g., adjusting the Carbon Nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility of P-FET and N-FET transistors. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state which saves power while the circuits are not in use. We show a more detailed application of our approach by designing a two-digit adder-subtractor circuit. We simulate the proposed ternary circuits using HSPICE via standard 32nm CNFET technology. The simulation results indicate the correct operation of the designs under different process, voltage and temperature (PVT) variations. Moreover, we designed a two-digit adder/subtractor and a power efficient ternary logic ALU based on the proposed gates. Simulation results show that the two-digit adder/subtractor using our proposed gates has 12X and 5X lower power consumption and PDP (power delay product) respectively, compared to previous designs.

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