scholarly journals Implementation of Unbalanced Ternary Logic Gates with the Combination of Spintronic Memristor and CMOS

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 542 ◽  
Author(s):  
Haifeng Zhang ◽  
Zhaowei Zhang ◽  
Mingyu Gao ◽  
Li Luo ◽  
Shukai Duan ◽  
...  
Keyword(s):  
High Efficiency ◽  
Load Capacity ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Logic Circuit ◽  
Oxide Semiconductor ◽  
Ternary Logic ◽  
Logic Operations ◽  
Almost All ◽  
Logic Functions

A memristor is a nanoscale electronic element that displays a threshold property, non-volatility, and variable conductivity. Its composite circuits are promising for the implementation of intelligence computation, especially for logic operations. In this paper, a flexible logic circuit composed of a spintronic memristor and complementary metal-oxide-semiconductor (CMOS) switches is proposed for the implementation of the basic unbalanced ternary logic gates, including the NAND, NOR, AND, and OR gates. Meanwhile, due to the participation of the memristor and CMOS, the proposed circuit has advantages in terms of non-volatility and load capacity. Furthermore, the input and output of the proposed logic are both constant voltages without signal degradation. All these three merits make the proposed circuit capable of realizing the cascaded logic functions. In order to demonstrate the validity and effectiveness of the entire work, series circuit simulations were carried out. The experimental results indicated that the proposed logic circuit has the potential to realize almost all basic ternary logic gates, and even some more complicated cascaded logic functions with a compact circuit construction, high efficiency, and good robustness.

Easily Cascaded Memristor-CMOS Hybrid Circuit for High-Efficiency Boolean Logic Implementation

2018 ◽  
Vol 28 (12) ◽  
pp. 1850149 ◽  
Author(s):  
Zhekang Dong ◽  
Donglian Qi ◽  
Yufei He ◽  
Zhao Xu ◽  
Xiaofang Hu ◽  
...  
Keyword(s):  
High Efficiency ◽  
Operating Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Boolean Logic ◽  
Oxide Semiconductor ◽  
Total Delay ◽  
Switching Dynamics ◽  
Two Phases ◽  
Logic Operations

Memristor is a novel passive electronic element with resistance-switching dynamics. Due to the threshold property and the variable conductivity of the memristive element, its composite circuits are promising for the implementation of logic operations. In this paper, a flexible logic circuit based on the threshold-type memristor and the mature complementary metal-oxide-semiconductor (CMOS) technology is designed for the realization of Boolean logic operations. Specifically, the proposed method is able to perform the NAND, AND, OR, and NOR gate operations through two phases, i.e. the writing operation and the reading operation. In such implementation, the total delay is very small especially for time-sequence inputs. Furthermore, for existing memristor-based logic implementation, a contrastive analysis with relevant computer simulations is carried out. The experimental results indicate that the proposed method is capable of realizing all basic Boolean logic operations, and some more complicated cascaded logic operations with more compact circuit structures, higher efficiency, and lower operating cost.

scholarly journals Complete Ring Artifacts Reduction Procedure for Lab-Based X-ray Nano CT Systems

Sensors ◽  
2021 ◽  
Vol 21 (1) ◽  
pp. 238
Author(s):  
Jakub Šalplachta ◽  
Tomáš Zikmund ◽  
Marek Zemek ◽  
Adam Břínek ◽  
Yoshihiro Takeda ◽  
...  
Keyword(s):  
High Efficiency ◽  
Image Inpainting ◽  
Simulated Data ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Detection Accuracy ◽  
Reduction Procedure ◽  
X Ray ◽  
Artifacts Reduction ◽  
Ct Data

In this article, we introduce a new ring artifacts reduction procedure that combines several ideas from existing methods into one complex and robust approach with a goal to overcome their individual weaknesses and limitations. The procedure differentiates two types of ring artifacts according to their cause and character in computed tomography (CT) data. Each type is then addressed separately in the sinogram domain. The novel iterative schemes based on relative total variations (RTV) were integrated to detect the artifacts. The correction process uses the image inpainting, and the intensity deviations smoothing method. The procedure was implemented in scope of lab-based X-ray nano CT with detection systems based on charge-coupled device (CCD) and scientific complementary metal–oxide–semiconductor (sCMOS) technologies. The procedure was then further tested and optimized on the simulated data and the real CT data of selected samples with different compositions. The performance of the procedure was quantitatively evaluated in terms of the artifacts’ detection accuracy, the comparison with existing methods, and the ability to preserve spatial resolution. The results show a high efficiency of ring removal and the preservation of the original sample’s structure.

scholarly journals CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

2018 ◽  
Vol 7 (2.7) ◽  
pp. 647
Author(s):  
J Lakshmi Prasanna ◽  
V Sahiti ◽  
E Raghuveera ◽  
M Ravi Kumar
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Tree Structure ◽  
Oxide Semiconductor ◽  
Least Significant Bit ◽  
Power Efficient ◽  
Prefix Tree ◽  
Digital Comparator ◽  
Parallel Prefix ◽  
Transmission Gates

A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs. 

scholarly journals All-optical modulation based on MoS2-Plasmonic nanoslit hybrid structures

Nanophotonics ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Feiying Sun ◽  
Changbin Nie ◽  
Xingzhan Wei ◽  
Hu Mao ◽  
Yupeng Zhang ◽  
...  
Keyword(s):  
High Efficiency ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Optical Modulator ◽  
Small Scale ◽  
Light Modulation ◽  
Optical Modulators ◽  
Signal Light ◽  
All Optical

Abstract Two-dimensional (2D) materials with excellent optical properties and complementary metal-oxide-semiconductor (CMOS) compatibility have promising application prospects for developing highly efficient, small-scale all-optical modulators. However, due to the weak nonlinear light-material interaction, high power density and large contact area are usually required, resulting in low light modulation efficiency. In addition, the use of such large-band-gap materials limits the modulation wavelength. In this study, we propose an all-optical modulator integrated Si waveguide and single-layer MoS2 with a plasmonic nanoslit, wherein modulation and signal light beams are converted into plasmon through nanoslit confinement and together are strongly coupled to 2D MoS2. This enables MoS2 to absorb signal light with photon energies less than the bandgap, thereby achieving high-efficiency amplitude modulation at 1550 nm. As a result, the modulation efficiency of the device is up to 0.41 dB μm−1, and the effective size is only 9.7 µm. Compared with other 2D material-based all-optical modulators, this fabricated device exhibits excellent light modulation efficiency with a micron-level size, which is potential in small-scale optical modulators and chip-integration applications. Moreover, the MoS2-plasmonic nanoslit modulator also provides an opportunity for TMDs in the application of infrared optoelectronics.

Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates

Circuit World ◽  
2019 ◽  
Vol 45 (4) ◽  
pp. 300-310
Author(s):  
Piyush Tankwal ◽  
Vikas Nehra ◽  
Sanjay Prajapati ◽  
Brajesh Kumar Kaushik
Keyword(s):  
Hall Effect ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Cmos Technology ◽  
Spin Transfer Torque ◽  
Spin Hall Effect ◽  
Oxide Semiconductor ◽  
Content Type

Purpose The purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM). Design/methodology/approach Spintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of charge. Two mechanisms, namely, STT and SHE, are used to switch the magnetization of MTJ. Findings It is observed that the power consumption in DSHE based logic gates is 95.6% less than the STT based gates. DSHE-based write circuit consumes only 5.28 fJ energy per bit. Originality/value This paper describes how the DSHE-MRAM is more effective for implementing logic circuits in comparison to STT-MRAM.

Logic Gates Design and Simulation Using Spatial Wavefunction Switched (SWS) FETs

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1550008 ◽  
Author(s):  
Bander Saman ◽  
P. Mirdha ◽  
M. Lingalugari ◽  
P. Gogna ◽  
F. C. Jain ◽  
...  
Keyword(s):  
Quantum Wells ◽  
Field Effect Transistors ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Behavioral Model ◽  
Charge Carrier Concentration ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
Proposed Model ◽  
High Band

This paper presents the design and modeling of logic gates using two channel spatial wavefunction switched field-effect transistors (SWSFETs) it is also known as a twin-drain MOSFET. In SWSFETs, the channel between source and drain has two or more quantum wells (QWs) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum wells layers and it causes the switching of charge carriers from one channel to other channel of the device. The first part of this paper shows the characteristics of n-channel SWSFET model, the second part provides the circuit topology for the SWSFET inverter and universal gates- NAND, AND, NOR,OR, XOR and XOR. The proposed model is based on integration between Berkeley Short-channel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level. The results show that all basic two-input logic gates can be implanted by using n-channel SWSFET only, It covers less area compared with CMOS (Complementary metal–oxide–semiconductor) gates. The NAND-NOR can be performed by three SWSFET, moreover the exclusive-NOR “XNOR” can be done by four SWSFET transistors also AND, OR, XOR gates require two additional SWSFET for inverting.

scholarly journals An Advanced 1-bit Arithmetic Logic Unit (ALU) with Hybrid Memristor-CMOS Architecture

2021 ◽  
Author(s):  
Muhammad Farhan Azmine ◽  
Urmi Debnath ◽  
Yeasir Arafat
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Building Blocks ◽  
Oxide Semiconductor ◽  
Memory Element ◽  
Area Efficiency ◽  
Arithmetic Logic Unit ◽  
Non Volatile Memory ◽  
Electrical Component ◽  
Logic Unit

<div>Memristor is dubbed as the fourth fundamental electrical component which works primarily as a non-volatile memory element. Memristors can also be used to construct logic gates, and Memristor Ratioed Logic (MRL) is one of these structures. The higher area efficiency and CMOS architecture compatibility of MRL gates have lead researchers to pay attention to its use in digital logic architecture. In this work, binary MRL is integrated with Complementary Metal-Oxide Semiconductor(CMOS) logic elements to develop building blocks of an Arithmetic Logic Unit (ALU). The proposed 1-bit ALU is simulated using LTSpice, which allows the versatility of changing the parameters as per the model used. This work designs and analyses an optimized cascadable 1-bit ALU with with voltage level based binary logic state via simulation. The proposed circuit shows improvement in transistor count and delay over benchmark circuits.</div>

scholarly journals Nanowire systems: technology and design

2014 ◽  
Vol 372 (2012) ◽  
pp. 20130102 ◽  
Author(s):  
Pierre-Emmanuel Gaillardon ◽  
Luca Gaetano Amarù ◽  
Shashikanth Bobba ◽  
Michele De Marchi ◽  
Davide Sacchetto ◽  
...  
Keyword(s):  
Large Scale ◽  
Field Effect Transistors ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Expressive Power ◽  
Oxide Semiconductor ◽  
Exclusive Or ◽  
20 Nm ◽  
Regular Arrays ◽  
Independent Gate

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-all-around structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity and thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology.

scholarly journals Modelling amorphous computations with transcription networks

2009 ◽  
Vol 6 (suppl_4) ◽  
Author(s):  
Zack Booth Simpson ◽  
Timothy L. Tsai ◽  
Nam Nguyen ◽  
Xi Chen ◽  
Andrew D. Ellington
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Nand Gate ◽  
Electronic Information ◽  
Logical Operations ◽  
Underlying Basis ◽  
Transcription Networks

The power of electronic computation is due in part to the development of modular gate structures that can be coupled to carry out sophisticated logical operations and whose performance can be readily modelled. However, the equivalences between electronic and biochemical operations are far from obvious. In order to help cross between these disciplines, we develop an analogy between complementary metal oxide semiconductor and transcriptional logic gates. We surmise that these transcriptional logic gates might prove to be useful in amorphous computations and model the abilities of immobilized gates to form patterns. Finally, to begin to implement these computations, we design unique hairpin transcriptional gates and then characterize these gates in a binary latch similar to that already demonstrated by Kim et al . (Kim, White & Winfree 2006 Mol. Syst. Biol. 2 , 68 (doi:10.1038/msb4100099)). The hairpin transcriptional gates are uniquely suited to the design of a complementary NAND gate that can serve as an underlying basis of molecular computing that can output matter rather than electronic information.

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