scholarly journals Implementation and Comparison of Radix-8 Booth Multiplier by using 32-bit Parallel prefix adders for High Speed Arithmetic Applications

2021 ◽  
Vol 12 (3) ◽  
pp. 5673-5683
Author(s):  
Barma Venkata RamaLakshmi Et. al.
Keyword(s):  
High Speed ◽  
High Performance ◽  
Digital Systems ◽  
High Demand ◽  
Major Drawback ◽  
Booth Multiplier ◽  
Computational Speed ◽  
Parallel Prefix ◽  
Simulation Results ◽  
Prefix Adders

This paper presents the implementation and design of  Radix-8 booth Multiplier using 32-bit parallel prefix adders. High performance processors have a high demand in the industrial market. For achieving high performance and to enhance the computational speed multiplier plays a key role in performance of digital system. But the major drawback is it consumes more power , area and delay. To enhance the performance and decrease the area consumption and delay there are many algorithms and techniques. In this paper we designed a radix-8 Booth Multiplier using two parallel prefix adders and compared them for best optimized multiplier. The number of parital products generation can be reduced by n/3 by using radix-8 in the multiplier encoding. To further reduce the additions we have used booth recoding mechanism .We have implemented the design using Kogge stone adder and Brent kung adder. We observed that by using parallel prefix adders reduces the delay further more which results in significant increase in speed of the digital systems. The simulation results are carried out on XILINX VIVADO software.

scholarly journals Low Power High Speed Arithmetic Circuits

2019 ◽  
Vol 8 (2) ◽  
pp. 807-813 ◽  
Keyword(s):  
Low Power ◽  
System Design ◽  
High Speed ◽  
Arithmetic Circuits ◽  
Booth Multiplier ◽  
Vedic Multiplier ◽  
Vlsi System ◽  
Parallel Prefix ◽  
Prefix Adders ◽  
Vlsi System Design

In the Design of arithmetic circuits reducing area, high speed and power are the major areas in VLSI system design. In this paper parallel prefix adders like Kogge-stone adder, Breunt-Kung adder, Ladner-Fischer adder is designed .Radix-4 Booth multiplier is designed by using Kogge-Stone adder. 16 bit Vedic multiplier is done by using Urdhwa Triyambaka sutra .8bit Vedic division is implemented by using Crumbs method so as to reduce the area, LUT tables and increase the speed as well as to reduce the Power dissipiation. The design is synthesized using Xilinx ISE 14.1 design suite.

scholarly journals Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders

2018 ◽  
Vol 7 (2) ◽  
pp. 115
Author(s):  
Nehru.K K ◽  
Nagarjuna T ◽  
Somanaidu U
Keyword(s):  
High Performance ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Transmission Technique ◽  
Look Ahead ◽  
Parallel Prefix ◽  
Prefix Adder ◽  
Signal Processors ◽  
Prefix Adders ◽  
Better Than

<span>Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes<strong> </strong>with the lowest transistor<strong> </strong>count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.</span>

Design and Analysis of Rotary Positive Displacement Mechanism for Oil-Less Compression

2010 ◽  
Author(s):  
Holger Roser
Keyword(s):  
High Speed ◽  
High Performance ◽  
Effective Means ◽  
Cost Effective ◽  
Industrial Applications ◽  
Two Phase ◽  
Major Drawback ◽  
Displacement Mechanism ◽  
Flow Losses ◽  
Positive Displacement

In this paper, a simple positive displacement mechanism is investigated, which comprises two counter-rotating meshing rotors within a casing. Although considered for various applications more than a century ago, the basic geometry of this mechanism has not been further explored or adapted to modern gas compressor technology. As a fully balanced rotational mechanism operating at uniform angular velocity, potential applications range from pumps to expanders, from slow large displacement to high-speed devices; nonetheless, this research focuses on high-performance oil-less gas compressors as an ideal application. During one complete cycle, the main rotor compresses and discharges the fluid, whilst the secondary rotor seals the compression chamber. Important features of this mechanism are the circular profiles of the rotors, the potential to accommodate large ports for reduced flow losses, and ease of cooling. The simple geometry facilitates a cost-effective means of achieving tight operating clearances between rotors and casing for enhanced sealing without the need for liquid lubricants such as oil. This study and preliminary tests indicate that pressure ratios suitable for standard industrial applications can be obtained over a broad speed range, whilst minimizing friction and flow losses, a major drawback of current technologies. Moreover, two-phase compression and injection of liquids prior to compression have been studied and identified as a means to further improve efficiency and cooling.

scholarly journals Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-18 ◽  
Author(s):  
Subodh Wairya ◽  
Rajendra Kumar Nagaria ◽  
Sudarshan Tiwari
Keyword(s):  
High Speed ◽  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Vlsi Design ◽  
Reducing Power ◽  
Full Adder ◽  
Process Models ◽  
Majority Function ◽  
Simulation Results

This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC 0.18 m process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.

scholarly journals Design a High Speed Multiplier using Two Phase PPA

2019 ◽  
Vol 8 (11S2) ◽  
pp. 146-149
Keyword(s):  
High Speed ◽  
Two Phase ◽  
Ripple Carry Adder ◽  
Product Generation ◽  
Different Types ◽  
Effective System ◽  
Parallel Prefix ◽  
Three Stages ◽  
Prefix Adder ◽  
Prefix Adders

Basically, multiplier is an efficient superconductor logic which performs various switching operation. Here different types of adders are analysed using different methodologies. In this paper we introduced a multiplier using proposed PPA. It uses parallel prefix adders in their reduction phase and it is an effective system for faster results and optimised. The entire operation of proposed system depends upon three stages they are multiplier partial product generation, reduction stages and parallel prefix adder which is discussed in below sections. The delay gets reduced by achieving low logical depth in the system. So the Proposed system reduces the delay. From the proposed system we can observe that there is a reduction in delay and complexity. Compared to ripple carry adder and carry save adder, proposed system gives better results.

scholarly journals Design of modified booth based multiplier with carry pre-computation

2019 ◽  
Vol 13 (3) ◽  
pp. 1048
Author(s):  
Chaitanya CVS ◽  
Sundaresan C ◽  
P R Venkateswaran ◽  
Keerthana Prasad
Keyword(s):  
High Speed ◽  
High Performance ◽  
Arithmetic Unit ◽  
Verilog Hdl ◽  
Complex Arithmetic ◽  
Booth Multiplier ◽  
Embedded Computer ◽  
Trade Offs ◽  
Vlsi Technology ◽  
Dsp Processors

Arithmetic unit is the most important component of modern embedded computer systems. Arithmetic unit generally includes floating point and fixed-point arithmetic operations and trigonometric functions. Multipliers units are the most important hardware structures in a complex arithmetic unit. With increase in chip frequency, the designer must be able to find the best set of trade-offs. The ability for faster computation is essential to achieve high performance in many DSP and Graphic processing algorithms and is why there is at least one dedicated Multiplier unit in all of the modern commercial DSP processors. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. A novel modified booth multiplier design for high speed VLSI applications using pre-computation logic has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.

scholarly journals Design and Implementation of High Speed Area Efficient Carry Select Adder Using Spanning Tree Adder Technique

2018 ◽  
pp. 21-26
Author(s):  
Hima Bindu Vykuntam ◽  
Chennaiah M ◽  
Sudhakar K
Keyword(s):  
Spanning Tree ◽  
High Speed ◽  
Computation Time ◽  
Digital Design ◽  
Comparative Performance ◽  
Ripple Carry Adder ◽  
Parallel Prefix ◽  
Carry Select Adder ◽  
Prefix Adder ◽  
Prefix Adders

In this paper, we propose Carry Select Adder (CSLA) architecture with parallel prefix adder. Instead of using 4-bit Brent Kung Adder (BKA), another parallel prefix adder i.e., 4-bit spanning Tree (ST) adder is used to design CSA. Because Adders are key element in digital design, which are not only performing addition operation, but also many other function such as subtraction, multiplication and division. A Ripple Carry Adder (RCA) gives the most complicated design as-well-as longer computation time so that we may gone for parallel prefix adders. This time critical application we use Spanning tree parallel prefix adder to drive fast results but they lead to increase in area. Proposed Carry Select Adder understands between RCA and BKA in term of area and delay. Delay of Existing adders is larger therefore we have replaced those with Brent Spanning Tree parallel prefix adder which gives fast result. This paper describes comparative performance of 4-bit RCA and 4-Bit BK parallel prefix adders with Our Proposed Spanning Tree adder based carry select adder designed using Xilinx ISE tool.

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