Study of immersion silver and tin printed-circuit-board surface finishes in lead-free solder applications

2004 ◽  
Vol 33 (9) ◽  
pp. 977-990 ◽  
Author(s):  
Minna Arra ◽  
Dongkai Shangguan ◽  
Dongji Xie ◽  
Janne Sundelin ◽  
Toivo Lepistö ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Printed Circuit ◽  
Surface Finishes ◽  
Board Surface ◽  
Free Solder ◽  
Immersion Silver

Reliability study of surface mount printed circuit board assemblies with lead‐free solder joints

2008 ◽  
Vol 20 (2) ◽  
pp. 30-38 ◽  
Author(s):  
Jeffery C.C. Lo ◽  
B.F. Jia ◽  
Z. Liu ◽  
J. Zhu ◽  
S.W. Ricky Lee
Keyword(s):  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Reliability Study ◽  
Surface Mount ◽  
Printed Circuit ◽  
Free Solder

Site Redressing Techniques and Rework of Lead-Free Chip Scale Packages

2003 ◽  
Author(s):  
Arun Gowda ◽  
Anthony Primavera ◽  
K. Srihari
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Printed Circuit ◽  
Free Solder ◽  
The Individual ◽  
Component Assembly ◽  
Free Area

The implementation of lead-free solder into an electronics assembly process necessitates the reassessment of the individual factors involved in component attachment and rework. A component assembly undergoes multiple thermal cycles during rework. With the use of lead-free solder, the assemblies are subjected to higher assembly and rework temperatures than those required for eutectic tin-lead assemblies. The rework of lead-free area array components involves the removal of defective component, preparation of the printed circuit board attachment pad (site redressing), solder paste replenishment or flux deposition, and component placement and reflow. This paper primarily focuses on the site redressing aspect of lead-free rework, followed by the development of rework processes for lead-free chip scale packages utilizing the knowledge gained in the site redressing studies.

Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board

2000 ◽  
Author(s):  
John H. Lau ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Shear Stress ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Wafer Level ◽  
Shear Creep ◽  
Printed Circuit ◽  
Chip Scale Package ◽  
Free Solder

Abstract In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. Two different lead-free solder alloys are considered, namely, 96.5wt%Sn-3.5wt%Ag and 100wt%In. The 62wt%Sn-36wt%Pb-2wt%Ag solder alloy is also considered to establish a baseline. All of these solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, and shear creep strain history at the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of lead-free solder bumped WLCSP on PCB assemblies. Also, the effects of microvia build-up PCB on the WLCSP solder joint reliability are investigated.

Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board

2002 ◽  
Vol 124 (2) ◽  
pp. 69-76 ◽  
Author(s):  
John H. Lau ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Shear Stress ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Wafer Level ◽  
Shear Creep ◽  
Printed Circuit ◽  
Chip Scale Package ◽  
Free Solder

In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. Two different lead-free solder alloys are considered, namely, 96.5wt percent Sn-3.5wt percent Ag and 100wt percent In. The 62wt percent Sn-36wt percent Pb-2wt percent Ag solder alloy is also considered to establish a baseline. All of these solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, and shear creep strain history at the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of lead-free solder bumped WLCSP on PCB assemblies. Also, the effects of microvia build-up PCB on the WLCSP Solder joint reliability are investigated.

Failure Analysis Techniques for Lead-Free Solder Joints

2005 ◽  
Author(s):  
Todd Castello ◽  
Dan Rooney ◽  
Dongkai Shangguan
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Board ◽  
Failure Modes ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Printed Circuit Board Assembly ◽  
Analysis Techniques ◽  
Solder Interconnects ◽  
Free Solder

Abstract Printed circuit board assembly with lead free solder is now a reality for most global electronics manufacturers. Extensive research and development has been conducted to bring lead free assembly processes to a demonstrated proficiency. Failure analysis has been an integral part of this effort and will continue to be needed to solve problems in volume production. Many failure analysis techniques can be directly applied to study lead free solder interconnects, while others may require some modification in order to provide adequate analysis results. In this paper, several of the most commonly applied techniques for solder joint failure analysis will be reviewed, including visual inspection, x-ray radiography, mechanical strength testing, dye & pry, metallography, and microscopy/photomicrography, comparing their application to lead bearing and lead free solder interconnects. Common failure modes and mechanisms will be described with examples specific to lead free solders, following PCB assembly as well as after accelerated reliability tests.

Reliability Analysis of Lead-Free Solder Joints with Solder Doping on Harsh Environment

2016 ◽  
Vol 2016 (1) ◽  
pp. 000117-000122 ◽  
Author(s):  
Cong Zhao ◽  
Thomas Sanders ◽  
Zhou Hai ◽  
Chaobo Shen ◽  
John L. Evans
Keyword(s):  
Surface Finish ◽  
Isothermal Aging ◽  
Electroless Nickel ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Surface Mount ◽  
Surface Finishes ◽  
Free Solder ◽  
Immersion Silver

Abstract This paper investigates the effect of long term isothermal aging and thermal cycling on the reliability of lead-free solder mixes with different solder compositions, PCB surface finishes, and isothermal aging conditions. A variety of surface mount components are considered, including ball grid arrays (BGAs), quad flat no-lead packages (QFNs) and 2512 Surface Mount Resistors (SMRs). 12 lead-free solder pastes are tested; for BGA packages these are reflowed with lead-free solder spheres of SAC105, SAC305 and matched doped solder spheres (“matched” solder paste and sphere composition). Three surface finishes are tested: Organic Solderability Preservative (OSP), Immersion Silver (ImAg), and Electroless Nickel Immersion Gold (ENIG). All test components are subjected to isothermal aging at 125°C for 0 or 12 months, followed by accelerated thermal cycle testing from −40°C to 125°C. Data from the first 1500 cycles is presented here, with a focus on the effect of surface finish on package reliability. Current results demonstrate that the choice of surface finish has a strong effect on reliability. However, different solder materials appear to show different reliability trends with respect to the surface finishes, and the reliability trends of BGA and SMR packages also diverge.

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