Improving Short Channel Effects by Reformed U-Channel UTBB FD SOI MOSFET: A Feasible Scaled Device

Silicon ◽  
2021 ◽  
Author(s):  
Moslem Ghassemi ◽  
Ali A. Orouji
Keyword(s):  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Channel Effects

Modeling of Sub Threshold Current and Sub Threshold Swing of Short-Channel Fully-Depleted SOI MOSFET with Back-Gate Control

2017 ◽  
Vol 9 (01) ◽  
pp. 67-72
Author(s):  
Sarvesh Dubey ◽  
Rahul Mishra
Keyword(s):  
Analytical Modeling ◽  
Threshold Current ◽  
Short Channel Effects ◽  
Short Channel ◽  
Simulation Data ◽  
Back Gate ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Effects ◽  
Gate Control

The present paper deals with the analytical modeling of subthreshold characteristics of short-channel fully-depleted recessed-source/drain SOI MOSFET with back-gate control. The variations in the subthreshold current and subthreshold swing have been analyzed against the back-gate bias voltage, buried-oxide (BOX) thickness and recessed source/drain thickness to assess the severity of short-channel effects in the device. The model results are validated by simulation data obtained from two-dimensional device simulator ATLAS from Silvaco.

Analytical Modeling for Short Channel SOI-MOSFET and to Study its Performance

2011 ◽  
Vol 110-116 ◽  
pp. 5150-5154
Author(s):  
K. Senthil Kumar ◽  
Saptarsi Ghosh ◽  
Anup Sarkar ◽  
S. Bhattacharya ◽  
Subir Kumar Sarkar
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Cmos Technology ◽  
Current Drive ◽  
Silicon On Insulator ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Silicon Bulk ◽  
Channel Effects

With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.

scholarly journals Impact of Split Gate in a Novel SOI MOSFET (SPG SOI) for Reduction of Short-Channel Effects: Analytical Modeling and Simulation

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Mohammad K. Anvarifard ◽  
Ali A. Orouji
Keyword(s):  
Step Function ◽  
Simulation Software ◽  
Silicon On Insulator ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Hot Carrier ◽  
Novel Device ◽  
Carrier Effect ◽  
Channel Effects

In this paper a comprehensive investigation of a novel device called split-gate silicon-on-insulator MOSFET (SPG SOI MOSFET) is proposed to reduce short-channel effects (SCEs). Studying the device has been done by analytical approach and simulation. In the proposed structure the gate is split into two parts. A voltage difference exists between the two parts. It is demonstrated that the surface potential in the channel region exhibits a step function. Some improvements are obtained on parameters such as SCEs, hot-carrier effect (HCE), and drain-induced barrier lowering (DIBL). The accuracy of the results obtained by use of the analytical model is verified by ATLAS device simulation software. The obtained results of the model are compared with those of the single-gate (SG) SOI MOSFET. The simulation results show that the SPG SOI MOSFET performance is superior.

Completely Surface-Potential-Based Compact Model of the Fully Depleted SOI-MOSFET Including Short-Channel Effects

2006 ◽  
Vol 53 (9) ◽  
pp. 2017-2024 ◽  
Author(s):  
N. Sadachika ◽  
D. Kitamaru ◽  
Y. Uetsuji ◽  
D. Navarro ◽  
M.M. Yusoff ◽  
...  
Keyword(s):  
Surface Potential ◽  
Compact Model ◽  
Short Channel Effects ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Effects

scholarly journals Π-Shape Silicon Window for Controlling OFF-Current in Junctionless SOI MOSFET

2021 ◽  
Author(s):  
Mahsa Mehrad ◽  
Meysam Zareiee
Keyword(s):  
The Body ◽  
Maximum Temperature ◽  
The Novel ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Buried Oxide ◽  
Novel Structure ◽  
Channel Effects ◽  
Channel Region

Abstract in this paper a modified junctionless transistor is proposed. The aim of the novel structure is controlling off-current using π-shape silicon window in the buried oxide under the source and the channel regions. The π-shape window changes the potential profile in the channel region in which the conduction band energy get away from the body Fermi energy and rebuild an electrostatic potential. Beside the significant reduced off-current, on current has acceptable value in the novel Silicon Region Junctionless MOSFET (SR-JMOSFET) than Conventional Junctionless MOSFET (C-JMOSFET). Moreover, replacing silicon material instead of silicon dioxide in the buried oxide causes reduced maximum temperature in the channel region. In this situation the heat could transfer to the π-shape silicon window and the temperature reduces in the active region, significantly.The simulation with the two-dimensional ATLAS simulator shows that short channel effects such as subthreshold and DIBL are controlled effectively in the SR-JMOSFET. Also, the optimum values of length and thickness of the π-shape window are defined to obtain the best behavior of the device.

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