scholarly journals Investigation of Short Channel Effects in SOI MOSFET with 20 nm Channel Length by a β-Ga2O3 Layer

2020 ◽  
Vol 9 (4) ◽  
pp. 045002 ◽  
Author(s):  
Dariush Madadi ◽  
Ali A. Orouji

MOSFET have been scaled down over the past few years in order to give rise to high circuit density and increase the speed of circuit. But scaling of MOSFET leads to issues such as poor control gate over the current which depends on gate voltage. Many short channel effects (SCE) influence the circuit performance and leads to the indeterminist response of drain current. These effects can be decreased by gate excitation or by using multiple gates and by offering better control gate the device parameters. In Single gate MOSFET, gate electric field decreases but multigate MOSFET or FinFET provides better control over drain current. In this paper, different FET structures such as MOSFET, TFET and FINFET are designed at 22nm channel length and effect of doping had been evaluated and studied. To evaluate the performance donor concentration is kept constant and acceptor concentration is varied.


2012 ◽  
Vol 7 (2) ◽  
pp. 137-144
Author(s):  
Rudolf T. Buhler ◽  
Renato Giacomini ◽  
Marcelo Antonio Pavanello ◽  
João Antonio Martino

Multiple-gate FETs is normally constructed on pre-etched silicon fins. These devices often present casual width variations along the silicon height; mostly caused by technological limitations of the fin definition process, due to non-ideal anisotropic etch. The resulting devices have, consequently, non-rectangular cross-sections, which can affect their electrical behavior. This work addresses the dependence of fin width non-uniformity on the occurrence of short-channel effects through comparative analysis, based on threedimensional numeric simulation of non-rectangular cross-section devices. The influence of the fin crosssection shape on electrical parameters showed to be dependent on channel length, becoming more sensible to the fin shape as the channel length is reduced, with better DC performance present on devices with bottom fin width smaller than top fin width due to the higher transconductance and lower output conductance, resulting on higher intrinsic voltage gain. For opposite fin shapes the total gate capacitance present higher values, beneficiating AC analog parameters, such as unit gain frequency.


Author(s):  
Sarvesh Dubey ◽  
Rahul Mishra

The present paper deals with the analytical modeling of subthreshold characteristics of short-channel fully-depleted recessed-source/drain SOI MOSFET with back-gate control. The variations in the subthreshold current and subthreshold swing have been analyzed against the back-gate bias voltage, buried-oxide (BOX) thickness and recessed source/drain thickness to assess the severity of short-channel effects in the device. The model results are validated by simulation data obtained from two-dimensional device simulator ATLAS from Silvaco.


2011 ◽  
Vol 110-116 ◽  
pp. 5150-5154
Author(s):  
K. Senthil Kumar ◽  
Saptarsi Ghosh ◽  
Anup Sarkar ◽  
S. Bhattacharya ◽  
Subir Kumar Sarkar

With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.


2021 ◽  
Vol 7 (1) ◽  
pp. 18-29
Author(s):  
Vinod Pralhad Tayade ◽  
Swapnil Laxman Lahudkar

In recent years, demands for high speed and low power circuits have been raised. As conventional metal oxide semiconductor field effect transistors (MOSFETs) are unable to satisfy the demands due to short channel effects, the purpose of the study is to design an alternative of MOSFETs. Graphene FETs are one of the alternatives of MOSFETs due to the excellent properties of graphene material. In this work, a user-defined graphene material is defined, and a graphene channel FET is implemented using the Silvaco technology computer-aided design (TCAD) tool at 100 nm and scaled to 20 nm channel length. A silicon channel MOSFET is also implemented to compare the performance. The results show the improvement in subthreshold slope (SS) = 114 mV/dec, ION/IOFF ratio = 14379, and drain induced barrier lowering (DIBL) = 123 mV/V. It is concluded that graphene FETs are suitable candidates for low power applications.


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