Comparative Analysis & Study of Various Leakage Reduction Techniques for Short Channel Devices in Junctionless Transistors: A Review and Perspective

Silicon ◽  
2021 ◽  
Author(s):  
Manish Kumar Rai ◽  
Abhinav Gupta ◽  
Sanjeev Rai
Keyword(s):  
Comparative Analysis ◽  
Short Channel ◽  
Analysis Study ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
Junctionless Transistors

scholarly journals Analysis of Leakage Reduction Techniques in Independent-Gate DG FinFET SRAM Cell

2013 ◽  
Vol 2013 ◽  
pp. 1-8
Author(s):  
Vandna Sikarwar ◽  
Saurabh Khandelwal ◽  
Shyam Akashe
Keyword(s):  
Research Work ◽  
Random Access ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Short Channel ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
Sram Cell ◽  
Channel Effects ◽  
Independent Gate

Scaling of devices in bulk CMOS technology leads to short-channel effects and increase in leakage. Static random access memory (SRAM) is expected to occupy 90% of the area of SoC. Since leakage becomes the major factor in SRAM cell, it is implemented using FinFET. Further, double-gate FinFET devices became a better choice for deep submicron technologies. With this consideration in our research work, 6T SRAM cell is implemented using independent-gate DG FinFET in which both the opposite sides of gates are controlled independently which provides better scalability to the SRAM cell. The device is implemented using different leakage reduction techniques such as gated-Vdd technique and multithreshold voltage technique to reduce leakage. Therefore, power consumption in the SRAM cell is reduced and provides better performance. Independent-gate FinFET SRAM cell using various leakage reduction techniques has been simulated using Cadence virtuoso tool in 45 nm technology.

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