scholarly journals A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique

Silicon ◽  
2021 ◽  
Author(s):  
D.S.Shylu Sam ◽  
D. Jackuline Moni ◽  
P. Sam Paul ◽  
D. Nirmal
Keyword(s):  
2021 ◽  
Author(s):  
Shylu Sam ◽  
D. Jackuline Moni ◽  
P.Sam Paul ◽  
D. Nirmal

Abstract This work presents a low power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon based CMOS process. Simultaneous capacitor sharing and op-amp sharing technique is used between two successive stages of a Sample-and Hold Ampifier (SHA) to reduce the power consumption.The memory effect in the proposed ADC is eliminated by a low input capacitance variable gm op-amp. The differential and integral nonlinearity of the converter are within LSB.Simulation results show that the required Signal-Furious-Dynamic range (SFDR) of 70dB, Signal-to -Noise-plus Distortion Ratio (SNDR) of 56.1dB and 9.02 Effective Number of Bits ( ENOB ) has been achieved with a 2MHz, 1-Vp−p,diff input signal while consuming only 7.3mW power from 1.8V supply.


2020 ◽  
Vol 12 (3) ◽  
pp. 168-174
Author(s):  
Rashmi Sahu ◽  
Maitraiyee Konar ◽  
Sudip Kundu

Background: Sensing of biomedical signals is crucial for monitoring of various health conditions. These signals have a very low amplitude (in μV) and a small frequency range (<500 Hz). In the presence of various common-mode interferences, biomedical signals are difficult to detect. Instrumentation amplifiers (INAs) are usually preferred to detect these signals due to their high commonmode rejection ratio (CMRR). Gain accuracy and CMRR are two important parameters associated with any INA. This article, therefore, focuses on the improvement of the gain accuracy and CMRR of a low power INA topology. Objective: The objective of this article is to achieve high gain accuracy and CMRR of low power INA by having high gain operational amplifiers (Op-Amps), which are the building blocks of the INAs. Methods: For the implementation of the Op-Amps and the INAs, the Cadence Virtuoso tool was used. All the designs and implementation were realized in 0.18 μm CMOS technology. Results: Three different Op-Amp topologies namely single-stage differential Op-Amp, folded cascode Op-Amp, and multi-stage Op-Amp were implemented. Using these Op-Amp topologies separately, three Op-Amp-based INAs were realized and compared. The INA designed using the high gain multistage Op-Amp topology of low-frequency gain of 123.89 dB achieves a CMRR of 164.1 dB, with the INA’s gain accuracy as good as 99%, which is the best when compared to the other two INAs realized using the other two Op-Amp topologies implemented. Conclusion: Using very high gain Op-Amps as the building blocks of the INA improves the gain accuracy of the INA and enhances the CMRR of the INA. The three Op-Amp-based INA designed with the multi-stage Op-Amps shows state-of-the-art characteristics as its gain accuracy is 99% and CMRR is as high as 164.1 dB. The power consumed by this INA is 29.25 μW by operating on a power supply of ±0.9V. This makes this INA highly suitable for low power measurement applications.


2010 ◽  
Vol 57 (3) ◽  
pp. 163-167 ◽  
Author(s):  
Jin-Fu Lin ◽  
Soon-Jyh Chang ◽  
Chun-Cheng Liu ◽  
Chih-Hao Huang

2013 ◽  
Vol 760-762 ◽  
pp. 54-59
Author(s):  
Yang Lin ◽  
Zhi Qun Li ◽  
Chen Jian Wu ◽  
Meng Zhang ◽  
Zeng Qi Wang

A fourth-order low-pass continuous-time filter for a WSN transmitter is presented. The active RC filter was chosen for the high linearity, designed by using the leapfrog topology imitates the passive filter. The operation amplifier (op-amp) adopted by the filter is feed-forward operation amplifier, which could get the GBW as large as possible under the low power consumption. The cut-off frequency deviation due to the process corner, aging and temperature deviation is adjusted by an automatic frequency tuning circuit. The filter in a 0.18μm RF CMOS technology consumes 1mW from a 1V power supply. The measured results of the chip show that the bandwidth is about 1.5MHz. The voltage gain of filter is about-4.5dB with the buffer, the ripple in the pass-band is lower than 0.5 dB, and the channel rejection ratio is larger than 30dB at 4MHz.


2017 ◽  
Vol 11 (6) ◽  
pp. 589-596 ◽  
Author(s):  
Anil Singh ◽  
Veena Rawat ◽  
Alpana Agarwal

2007 ◽  
Vol 54 (4) ◽  
pp. 1195-1200 ◽  
Author(s):  
J. Bouvier ◽  
Mokrane Dahoumane ◽  
Daniel Dzahini ◽  
J. Y. Hostachy ◽  
E. Lagorio ◽  
...  

Author(s):  
Naheem Olakunle Adesina ◽  
Md Azmot Ullah Khan ◽  
Jian Xu

2019 ◽  
Vol 66 (9) ◽  
pp. 3352-3364
Author(s):  
Mohammad H. Naderi ◽  
Chulhyun Park ◽  
Suraj Prakash ◽  
Martin Kinyua ◽  
Eric G. Soenen ◽  
...  
Keyword(s):  
Class Ab ◽  

2014 ◽  
Vol 106 (18) ◽  
pp. 36-38
Author(s):  
Bhanu KumarG ◽  
Vasudeva Reddy T
Keyword(s):  

Sign in / Sign up

Export Citation Format

Share Document