scholarly journals A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC using Simultaneous Capacitor and Op-amp Sharing Technique

2021 ◽  
Author(s):  
Shylu Sam ◽  
D. Jackuline Moni ◽  
P.Sam Paul ◽  
D. Nirmal
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Effective Number ◽  
Op Amp ◽  
Integral Nonlinearity ◽  
Silicon Based ◽  
Variable G

Abstract This work presents a low power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon based CMOS process. Simultaneous capacitor sharing and op-amp sharing technique is used between two successive stages of a Sample-and Hold Ampifier (SHA) to reduce the power consumption.The memory effect in the proposed ADC is eliminated by a low input capacitance variable gm op-amp. The differential and integral nonlinearity of the converter are within LSB.Simulation results show that the required Signal-Furious-Dynamic range (SFDR) of 70dB, Signal-to -Noise-plus Distortion Ratio (SNDR) of 56.1dB and 9.02 Effective Number of Bits ( ENOB ) has been achieved with a 2MHz, 1-Vp−p,diff input signal while consuming only 7.3mW power from 1.8V supply.

A LOW-VOLTAGE LOW-POWER 10-BIT 200 MS/S PIPELINED ADC IN 90 NM CMOS

2010 ◽  
Vol 19 (02) ◽  
pp. 393-405 ◽  
Author(s):  
SAHEL ABDINIA ◽  
MOHAMMAD YAVARI
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Pipeline Adc ◽  
Class A ◽  
Reduction Techniques ◽  
Dynamic Comparators

This paper presents a low-power 10-bit 200 MS/s pipelined ADC in a 90 nm CMOS technology with 1 V supply voltage. To decrease the power dissipation efficiently, a new architecture using a combination of two power reduction techniques named double-sampling and opamp-sharing has been used to reduce the power consumption significantly, without any degradation in the performance of the ADC. In addition, the stage scaling technique has been applied to the ADC efficiently, and two-stage class A/AB and class A amplifiers and dynamic comparators have been used in sample and hold and sub-ADCs. According to HSPICE simulation results, the 10-bit 200 MSample/s pipeline ADC with a 9.375 MHz, 1-VP-P,diff input signal in a 90 nm CMOS process achieves a SNDR of 58.5 dB while consuming only 30.9 mW power from a 1 V supply voltage.

scholarly journals A Switched-MOSFET Programmable Low-Voltage Filter

2004 ◽  
Vol 1 (1) ◽  
pp. 32-37
Author(s):  
Luís Cléber C. Marques ◽  
Wouter A. Serdijn
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Total Current ◽  
Sampled Data ◽  
Current Consumption ◽  
Digitally Programmable ◽  
Low Supply Voltage

This paper describes a digitally programmable low-voltage low-power analogue filter that can be used in hearing-aid circuits. The filter employs the recently introduced switched-MOSFET technique, a sampled-data technique suitable for low supply voltage operation since it avoids the conduction gap of the switches and does not need any dedicated process. The filter was implemented using the DIMES 1.6μm CMOS process and achieves 64 dB dynamic range. The total current consumption, drawn from a 2.2V supply, equals 93μA.

A 100-MS/s CMOS Sample-and-Hold Circuit with Input Common Mode Feedback

2013 ◽  
Vol 748 ◽  
pp. 847-852
Author(s):  
Jun Yang ◽  
Hong Hui Deng ◽  
Rui Zhang ◽  
Yong Sheng Yin
Keyword(s):  
High Performance ◽  
Dynamic Range ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Sample And Hold ◽  
Feedback Capacitor

A high performance sample-and-hold (S/H) circuit with input common mode feedback (ICMFB) is presented. The ICMFB is used to ensure that the input common mode voltage for the sample-and-hold amplifier (SHA) is maintained at a known value during the hold phase of operation in order to reduce the differential output error when the sample capacitor and feedback capacitor has mismatch. Meanwhile, bootstrapped switches are used to lower the switch on-resistance and reduce the effect of switch non-idealities. Then a low power two stage high gain wideband SHA is designed to guarantee the holding accuracy. Hspice simulated results based on SMIC 0.13μm 1P5M CMOS process under 1.2V supply voltage shows a 108.4 dB spurious free dynamic range (SFDR) at Nyquist input @Fs=100MS/s. The designed S/H circuit has been used in the front end of 14-bit 100MS/s Pipelined ADC adapted for single-ended applications.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

scholarly journals A Four-Channel Low-Noise Readout IC for Air Flow Measurement Using Hot Wire Anemometer in 0.18 μm CMOS Technology

Sensors ◽  
2021 ◽  
Vol 21 (14) ◽  
pp. 4694
Author(s):  
Kyeongsik Nam ◽  
Hyungseup Kim ◽  
Yongsu Kwon ◽  
Gyuri Choi ◽  
Taeyup Kim ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Air Flow ◽  
Low Noise ◽  
Cmos Process ◽  
Significant Information ◽  
Flow Measurements ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Op Amp ◽  
Noise Characteristics

Air flow measurements provide significant information required for understanding the characteristics of insect movement. This study proposes a four-channel low-noise readout integrated circuit (IC) in order to measure air flow (air velocity), which can be beneficial to insect biomimetic robot systems that have been studied recently. Instrumentation amplifiers (IAs) with low-noise characteristics in readout ICs are essential because the air flow of an insect’s movement, which is electrically converted using a microelectromechanical systems (MEMS) sensor, generally produces a small signal. The fundamental architecture employed in the readout IC is a three op amp IA, and it accomplishes low-noise characteristics by chopping. Moreover, the readout IC has a four-channel input structure and implements an automatic offset calibration loop (AOCL) for input offset correction. The AOCL based on the binary search logic adjusts the output offset by controlling the input voltage bias generated by the R-2R digital-to-analog converter (DAC). The electrically converted air flow signal is amplified using a three op amp IA, which is passed through a low-pass filter (LPF) for ripple rejection that is generated by chopping, and converted to a digital code by a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). Furthermore, the readout IC contains a low-dropout (LDO) regulator that enables the supply voltage to drive digital circuits, and a serial peripheral interface (SPI) for digital communication. The readout IC is designed with a 0.18 μm CMOS process and the current consumption is 1.886 mA at 3.3 V supply voltage. The IC has an active area of 6.78 mm2 and input-referred noise (IRN) characteristics of 95.4 nV/√Hz at 1 Hz.

A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications

2018 ◽  
Vol 27 (07) ◽  
pp. 1850104 ◽  
Author(s):  
Yuwadee Sundarasaradula ◽  
Apinunt Thanachayanont
Keyword(s):  
Low Power ◽  
Biomedical Applications ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Low Noise ◽  
Power Supply Voltage ◽  
Wide Dynamic Range ◽  
Dc Offset ◽  
Limiting Amplifier ◽  
Logarithmic Amplifier

This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18[Formula: see text][Formula: see text]m CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027[Formula: see text]mm2. The overall circuit consumes 9.75[Formula: see text][Formula: see text]W from a single 1.5[Formula: see text]V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80[Formula: see text]dB input dynamic range (from 10[Formula: see text][Formula: see text]V to 100[Formula: see text]mV), a bandwidth of 4[Formula: see text]Hz–10[Formula: see text]kHz, and a total input-referred noise of 5.52[Formula: see text][Formula: see text]V.

scholarly journals A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Spurious Free Dynamic Range ◽  
Time Interleaved ◽  
Free Dynamic

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

A ΣΔ MODULATOR USING GAIN-BOOST CLASS-C INVERTER FOR AUDIO APPLICATIONS

2013 ◽  
Vol 22 (10) ◽  
pp. 1340024
Author(s):  
HAO LUO ◽  
YAN HAN ◽  
RAY C. C. CHEUNG ◽  
TIANLIN CAO ◽  
XIAOPENG LIU ◽  
...  
Keyword(s):  
High Resolution ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Process ◽  
Signal To Noise ◽  
Dc Gain ◽  
Micro Power ◽  
Class C ◽  
On Chip ◽  
Σδ Modulator

This paper provides an audio 2-1 cascaded ΣΔ modulator using a novel gain-boost class-C inverter. The gain-boost class-C inverter behaves as a subthreshold amplifier. By introducing a gain-boost module, the inverter DC-gain is increased from 48 dB to 67 dB. The gain-boost class-C inverter consumes 57 μW at 1.2-V supply, where the gain-boost module consumes only 3 μW. In addition, an on-chip body bias technique is introduced to compensate the process and supply voltage variations of the class-C inverter. The proposed inverter-based ΣΔ modulator chip is implemented in 0.13-μm CMOS process, and achieves 86-dB peak-signal to noise and distortion ratio (SNDR) and 90-dB dynamic range (DR) over 22.05-KHz bandwidth at 1.2-V supply consuming 360 μW, which demonstrates that the gain-boost class-C inverter is particularly suitable for micro-power high-resolution applications.

scholarly journals Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

2019 ◽  
pp. 19-23
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Clock Signal ◽  
Voltage Level ◽  
Rfid Tag ◽  
Low Phase Noise

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.

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