Mechanical behaviour of silicon-silicon carbide composites

1996 ◽  
Vol 16 (7) ◽  
pp. 703-712 ◽  
Author(s):  
E. Scafè ◽  
G. Giunta ◽  
L. Fabbri ◽  
L. Di Rese ◽  
G. De Portu ◽  
...  
1998 ◽  
Vol 512 ◽  
Author(s):  
C. Koitzscht ◽  
M. O'Brient ◽  
D. Johri ◽  
A. Stoltzt ◽  
R. Nemanicht

ABSTRACTPhotoemission spectroscopy (UPS) was used to investigate the interface properties of deposited silicon on hexagonal 6H-silicon carbide. SiC cleaned in Si flux from a molecular beam epitaxy (MBE) system was used for this study. All processes were accomplished in an ultra high vacuum integrated system that allowed all cleaning, deposition, and analysis to be completed without exposure to ambient atmosphere. Thicknesses of sub- to multiple monolayers were deposited and the valence band structure was investigated. The valence band maximum (VBM) was observed to shift for Si depositions greater than 1 monolayer. The VBM offset was determined to be 2.4eV for a layer of 60Å Si on SiC. Furthermore, the prominent surface state feature of the silicon carbide (0001)si surface is reduced after Si deposition. The results are discussed in terms of the electronic properties of the Si – SiC interface.


2010 ◽  
Vol 2010 (HITEC) ◽  
pp. 000305-000309 ◽  
Author(s):  
Vinayak Tilak ◽  
Cheng-Po Chen ◽  
Peter Losee ◽  
Emad Andarawis ◽  
Zachary Stum

Silicon carbide based ICs have the potential to operate at temperatures exceeding that of conventional semiconductors such as silicon. Silicon carbide (SiC) based MOSFETs and ICs were fabricated and measured at room temperature and 300°C. A common source amplifier was fabricated and tested at room temperature and high temperature. The gain at room temperature and high temperature was 7.6 and 6.8 respectively. A SiC MOSFET based operational amplifier was also fabricated and tested at room temperature and 300°C. The small signal open loop gain at 1kHz was 60 dB at room temperature and 57 dB at 300°C. Long term stability testing at 300°C of the MOSFET and common source amplifiers showed very little drift.


1998 ◽  
Vol 27 (4) ◽  
pp. 296-299 ◽  
Author(s):  
J. P. Henning ◽  
K. J. Schoen ◽  
M. R. Melloch ◽  
J. M. Woodall ◽  
J. A. Cooper

2004 ◽  
Vol 82 (11) ◽  
pp. 3251-3253 ◽  
Author(s):  
Dong-Woo Shin ◽  
Sam Shik Park ◽  
Yong-Ho Choa ◽  
Koichi Niihara

2001 ◽  
Vol 687 ◽  
Author(s):  
Dongwon Choi ◽  
Robert J. Shinavski ◽  
Wayne S. Steffier ◽  
Skip Hoyt ◽  
S.Mark Spearing

AbstractA MEMS-based gas turbine engine is being developed for use as a button-sized portable power generator or micro-aircraft propulsion source. Power densities expected for the micro- engine require high combustor exit temperatures (1300-1700K) and very high rotor peripheral speeds (300-600m/s). These harsh operating conditions induce high stress levels in the engine structure, and thus require refractory materials with high strength. Silicon carbide has been chosen as the most promising material for use in the near future due to its high strength and chemical inertness at elevated temperatures. However, techniques for microfabricating single- crystal silicon carbide to the level of high precision needed for the micro-engine are not currently available. To circumvent this limitation and to take advantage of the well-established precise silicon microfabrication technologies, silicon-silicon carbide (SiC) hybrid turbine structures are being developed using chemical vapor deposition of poly-SiC on silicon wafers and wafer bonding processes. Residual stress control of SiC coatings is of critical importance to all the silicon-silicon carbide hybrid structure fabrication steps since a high level of residual stresses causes wafer cracking during the planarization, as well as excessive wafer bow, which is detrimental to the subsequent planarization and bonding processes. The origins of the residual stresses in CVD SiC layers have been studied. SiC layers (as thick as 30µm) with low residual stresses (on the order of several tens of MPa) have been produced by controlling CVD process parameters such as temperature and gas ratio. Wafer-level SiC planarization has been accomplished by mechanical polishing using diamond grit and bonding processes are currently under development using interlayer materials such as silicon dioxide or poly-silicon. These process development efforts will be reviewed in the context of the overall micro-engine development program.


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