Field-programmable biological circuits and configurable (bio)logic blocks for distributed biological computing

Test Pattern ◽

Fault Coverage ◽

Area Overhead ◽

Field Programmable ◽

Self Test ◽

Gate Array ◽

Built In Self Test ◽

Pattern Generators ◽

This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.

Technology Mapping of FSM Oriented to LUT-Based FPGA

Applied Sciences ◽

10.3390/app10113926 ◽

2020 ◽

Vol 10 (11) ◽

pp. 3926

Author(s):

Marcin Kubica ◽

Dariusz Kania

Keyword(s):

Finite State Machine ◽

Synthesis Method ◽

Technology Mapping ◽

Look Up Table ◽

Finite State ◽

Field Programmable ◽

Simultaneous Synthesis ◽

Transition Block ◽

The main purpose of the paper is to present technology mapping of FSM (finite state machine) oriented to LUT (look-up table)-based FPGA (field-programmable gate array). The combinational part of an automaton, which consists of a transition block and an output block, was mapped in LUT-based logic blocks. In the paper, the idea of carrying out the combinational part of FSM was presented and leads to the reduction of the number of LUTs needed to carry out an automaton. The essence of this method is a simultaneous synthesis of the whole combinational block described in the form of multi-output function. The proposed idea makes it possible to conduct decomposition that may enable to share logic blocks, which can lead to the reduction of using resources of FPGA. The decomposition process was conducted using the analyzed DECOMP system. The effectiveness of the proposed idea of the FSM description was also confirmed by conducting decomposition with the usage of the ABC system. The obtained results prove the efficiency of the proposed synthesis method of FSM in comparison with the separate synthesis of a transition block and an output block.

A Novel Fault Orientation Technique of FPGA Configurable Logic Blocks Based on Improved Shift Register

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.347-350.1602 ◽

2013 ◽

Vol 347-350 ◽

pp. 1602-1606

Author(s):

Jun Bin Zhang ◽

Jin Yan Cai ◽

Dan Yang Li

Keyword(s):

Design Theory ◽

Shift Register ◽

Fault Diagnose ◽

Test Technique ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Orientation Technique ◽

Important Significance ◽

With the development of digital integrate circuit system which is based on Field Programmable Gate Arrays (FPGA), the request on FPGA test technique is becoming higher and higher. The Boundary Scan Technique and Built-In Self-Test (BIST) technique appear in succession, however, these techniques dont implement Configurable Logic Block (CLB) fault diagnose and fault orientation. Arrays-based technique was advanced, which also have some problems about masking of faults and too many reconfiguration times. According to these problems, A Novel Shift Register-based technique for Fault Orientation of FPGA Configurable Logic Blocks was advanced. The paper analyses the design theory about core circuit configure, and has important significance impact on Fault Orientation of FPGA Configurable Logic Blocks.

2011 IEEE International Conference on Computer Science and Automation Engineering ◽

Efficient approach to design low power reversible logic blocks for Field Programmable Gate Arrays

10.1109/csae.2011.5952845 ◽

2011 ◽

Cited By ~ 6

Author(s):

Abu Sadat Md. Sayem ◽

Sajib Kumar Mitra

Keyword(s):

Low Power ◽

Field Programmable Gate Arrays ◽

Reversible Logic ◽

Efficient Approach ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921) ◽

Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits

10.1109/fpt.2004.1393260 ◽

2005 ◽

Cited By ~ 4

Author(s):

A.G. Ye ◽

J. Rose

Keyword(s):

Field Programmable ◽

Datapath Circuits ◽

Gate Array ◽

Array Density ◽

Architecture Design and Field Programmable Gate Array Implementation of Removable Visible Image Watermarking for Digital Camera Images Using a Private Key

Journal of Imaging Science and Technology ◽

10.2352/j.imagingsci.technol.2014.58.6.060502 ◽

2014 ◽

Vol 58 (6) ◽

pp. 605021-6050210

Author(s):

P. L. Ajitha Merlin ◽

V. Rajamani ◽

V. E. Jayanthi

Keyword(s):

Image Watermarking ◽

Digital Camera ◽

Architecture Design ◽

Visible Image ◽

Private Key ◽

Field Programmable ◽

Gate Array

Memory Requirement Reduction of Deep Neural Networks for Field Programmable Gate Arrays Using Low-Bit Quantization of Parameters

2020 28th European Signal Processing Conference (EUSIPCO) ◽

10.23919/eusipco47968.2020.9287739 ◽

2021 ◽

Author(s):

Niccolo Nicodemo ◽

Gaurav Naithani ◽

Konstantinos Drossos ◽

Tuomas Virtanen ◽

Roberto Saletti

Keyword(s):

Neural Networks ◽

Deep Neural Networks ◽

Field Programmable Gate Arrays ◽

Memory Requirement ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

Rapid prototyping of algorithmic A/D converters based on FPAA devices

Bulletin of the Polish Academy of Sciences Technical Sciences ◽

10.2478/bpasts-2013-0073 ◽

2013 ◽

Vol 61 (3) ◽

pp. 691-696 ◽

Cited By ~ 4

Author(s):

R. Suszynski ◽

K. Wawryn

Keyword(s):

Rapid Prototyping ◽

Sinusoidal Signal ◽

Digital Converter ◽

Mixed Signal ◽

Analog Digital Converter ◽

Signal Systems ◽

Programmable Analog ◽

Field Programmable ◽

Field Programmable Analog Array

Abstract A rapid prototyping method for designing mixed signal systems has been presented in the paper. The method is based on implementation of the field programmable analog array (FPAA) to configure and reconfigure mixed signal systems. A serial algorithmic analog digital converter has been used as an example. Three converter architectures have been selected and implemented FPAA device. To verify and illustrate converters operation and prototyping capabilities, implemented converters have been excited by a sinusoidal signal. Analog sinusoidal excitations, digital responses and sinusoidal waveforms after reconstruction are presented.