EKV3 compact modeling of MOS transistors from a 0.18μm CMOS technology for mixed analog–digital circuit design at low temperature

Arithmetic operations play a major role in digital circuit design like adders, multipliers etc. Multiplication is an important fundamental arithmetic operation in high performance systems such as microprocessor and digital signal processors circuits. Implementation of multipliers using compressor circuit over conventional adders will reduce the number of levels of addition, which will in turn reduces the latency of the multiplier. Multiplier module is most likely the essential part of MAC (Multiplier-Accumulator) unit design. Compressor based multipliers in MAC architecture design results high performance. FPGA and ASIC implementations of 4:2 compressor based 32-bit Wallace and Dadda multipliers can be done by using Xilinx Vivado and Cadence CMOS technology tools. These results are compared with other multiplier designs with respect to area, latency and power dissipation.

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SINUSOIDAL CLOCKED SENSE-AMPLIFIER-BASED ENERGY RECOVERY FLIP-FLOPS

Journal of Circuits System and Computers ◽

10.1142/s0218126614500662 ◽

2014 ◽

Vol 23 (05) ◽

pp. 1450066

Author(s):

JITENDRA KANUNGO ◽

S. DASGUPTA

Keyword(s):

Low Power ◽

Circuit Design ◽

Energy Recovery ◽

Cmos Technology ◽

Digital Circuit ◽

Flip Flop ◽

Ultra Low Power ◽

Sense Amplifier ◽

Simulation Based ◽

Digital Circuit Design

Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-amplifier based flip-flop (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed flip-flop operating with energy recovery single phase sinusoidal clock shows better performance. The proposed flip-flop also reduces the leakage current and glitch.

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Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style

Journal of Engineering ◽

10.1155/2016/8027150 ◽

2016 ◽

Vol 2016 ◽

pp. 1-10

Author(s):

Neeta Pandey ◽

Damini Garg ◽

Kirti Gupta ◽

Bharat Choudhary

Keyword(s):

Circuit Design ◽

High Speed ◽

Current Mode ◽

Cmos Technology ◽

Digital Circuit ◽

Mixed Signal ◽

Current Mode Logic ◽

Digital Circuit Design ◽

Pass Transistor ◽

Logic Functions

This paper proposes hybrid dynamic current mode logic (H-DyCML) as an alternative to existing dynamic CML (DyCML) style for digital circuit design in mixed-signal applications. H-DyCML introduces complementary pass transistors for implementation of logic functions. This allows reduction in the stacked source-coupled transistor pair levels in comparison to the existing DyCML style. The resulting reduction in transistor pair levels permits significant speed improvement. SPICE simulations using TSMC 180 nm and 90 nm CMOS technology parameters are carried out to verify the functionality and to identify their advantages. Some issues related to the compatibility of the complementary pass transistor logic have been investigated and the appropriate solutions have been proposed. The performance of the proposed H-DyCML gates is compared with the existing DyCML gates. The comparison confirms that proposed H-DyCML gates is faster than the existing DyCML gates.

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