scholarly journals Design and Implementation of Compressor based 32-bit Multipliers for MAC Architecture

2019 ◽  
Vol 8 (9) ◽  
pp. 2007-2014
Keyword(s):  
Circuit Design ◽  
High Performance ◽  
Arithmetic Operation ◽  
Digital Signal ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Digital Circuit Design ◽  
Unit Design ◽  
High Performance Systems ◽  
Signal Processors

Arithmetic operations play a major role in digital circuit design like adders, multipliers etc. Multiplication is an important fundamental arithmetic operation in high performance systems such as microprocessor and digital signal processors circuits. Implementation of multipliers using compressor circuit over conventional adders will reduce the number of levels of addition, which will in turn reduces the latency of the multiplier. Multiplier module is most likely the essential part of MAC (Multiplier-Accumulator) unit design. Compressor based multipliers in MAC architecture design results high performance. FPGA and ASIC implementations of 4:2 compressor based 32-bit Wallace and Dadda multipliers can be done by using Xilinx Vivado and Cadence CMOS technology tools. These results are compared with other multiplier designs with respect to area, latency and power dissipation.

Aplicação do Filtro de Kalman Estendido com matrizes pré sintonizadas ao acionamento sensorless de motores de indução

2020 ◽  
Author(s):  
Leonardo De Magalhães Lopes ◽  
Zélia Myriam Assis Peixoto
Keyword(s):  
High Performance ◽  
Digital Signal ◽  
Control Technique ◽  
Reduced Order ◽  
Variance Matrix ◽  
Ac Electric Drive ◽  
Three Phase ◽  
High Performance Systems ◽  
Drive Systems ◽  
Signal Processors

Sensorless control methods stand out as an alternative for cost reduction and maintenance in AC electric drive systems. This work deals with the application of the Extended Kalman Filter (EKF) to the estimation of the speed and position of the rotor aiming at the implementation of the indirect vector control technique in a speed control system for three- phase induction motors. The Kalman lter, despite its mathematical and computational complexity, performs well under variable speed and load conditions as well as convergence times consistent with the usual requirements of high performance systems. The main contributions of this work are the use of a reduced-order EKF (ROEKF) and the co-variance matrix pretuning in order to accelerate the convergence in the velocity and position estimates for futureimplementations in digital signal processors currently accessible.

SINUSOIDAL CLOCKED SENSE-AMPLIFIER-BASED ENERGY RECOVERY FLIP-FLOPS

2014 ◽  
Vol 23 (05) ◽  
pp. 1450066
Author(s):  
JITENDRA KANUNGO ◽  
S. DASGUPTA
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Energy Recovery ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Sense Amplifier ◽  
Simulation Based ◽  
Digital Circuit Design

Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-amplifier based flip-flop (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed flip-flop operating with energy recovery single phase sinusoidal clock shows better performance. The proposed flip-flop also reduces the leakage current and glitch.

Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques

2020 ◽  
Vol 17 (4) ◽  
pp. 1595-1599
Author(s):  
N. Suresh ◽  
K. Subba Rao ◽  
R. Vassoudevan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Large Scale ◽  
Digital Signal ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Essential Components

Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.

scholarly journals Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style

2016 ◽  
Vol 2016 ◽  
pp. 1-10
Author(s):  
Neeta Pandey ◽  
Damini Garg ◽  
Kirti Gupta ◽  
Bharat Choudhary
Keyword(s):  
Circuit Design ◽  
High Speed ◽  
Current Mode ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Mixed Signal ◽  
Current Mode Logic ◽  
Digital Circuit Design ◽  
Pass Transistor ◽  
Logic Functions

This paper proposes hybrid dynamic current mode logic (H-DyCML) as an alternative to existing dynamic CML (DyCML) style for digital circuit design in mixed-signal applications. H-DyCML introduces complementary pass transistors for implementation of logic functions. This allows reduction in the stacked source-coupled transistor pair levels in comparison to the existing DyCML style. The resulting reduction in transistor pair levels permits significant speed improvement. SPICE simulations using TSMC 180 nm and 90 nm CMOS technology parameters are carried out to verify the functionality and to identify their advantages. Some issues related to the compatibility of the complementary pass transistor logic have been investigated and the appropriate solutions have been proposed. The performance of the proposed H-DyCML gates is compared with the existing DyCML gates. The comparison confirms that proposed H-DyCML gates is faster than the existing DyCML gates.

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

2008 ◽  
Vol 96 (2) ◽  
pp. 343-365 ◽  
Author(s):  
B.H. Calhoun ◽  
Yu Cao ◽  
Xin Li ◽  
Ken Mai ◽  
L.T. Pileggi ◽  
...  
Keyword(s):  
Circuit Design ◽  
Digital Circuit ◽  
Nanoscale Cmos ◽  
Digital Circuit Design ◽  
Challenges And Opportunities ◽  
Design Challenges

scholarly journals Embedded GPU Implementation for High-Performance Ultrasound Imaging

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 884
Author(s):  
Stefano Rossi ◽  
Enrico Boni
Keyword(s):  
High Performance ◽  
Graphics Processing Unit ◽  
Digital Signal ◽  
Processing Unit ◽  
Embedded Computing ◽  
Field Programmable ◽  
Peripheral Component Interconnect ◽  
Programmable Gate Arrays ◽  
Graphics Processing ◽  
Signal Processors

Methods of increasing complexity are currently being proposed for ultrasound (US) echographic signal processing. Graphics Processing Unit (GPU) resources allowing massive exploitation of parallel computing are ideal candidates for these tasks. Many high-performance US instruments, including open scanners like ULA-OP 256, have an architecture based only on Field-Programmable Gate Arrays (FPGAs) and/or Digital Signal Processors (DSPs). This paper proposes the implementation of the embedded NVIDIA Jetson Xavier AGX module on board ULA-OP 256. The system architecture was revised to allow the introduction of a new Peripheral Component Interconnect Express (PCIe) communication channel, while maintaining backward compatibility with all other embedded computing resources already on board. Moreover, the Input/Output (I/O) peripherals of the module make the ultrasound system independent, freeing the user from the need to use an external controlling PC.

A MOS Transistor Model for Mixed Analog-digital Circuit Design and Simulation

2006 ◽  
pp. 49-95 ◽  
Author(s):  
Matthias Bucher ◽  
Christophe Lallement ◽  
François Krummenacher ◽  
Christian Enz
Keyword(s):  
Circuit Design ◽  
Digital Circuit ◽  
Mos Transistor ◽  
Digital Circuit Design ◽  
Transistor Model
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