A single grain boundary parameter to characterize normal stress fluctuations in materials with elastic cubic grains

2021 ◽  
Vol 89 ◽  
pp. 104293
Author(s):  
S. El Shawish ◽  
T. Mede ◽  
J. Hure
2002 ◽  
Vol 715 ◽  
Author(s):  
Sang-Hoon Jung ◽  
Jae-Hoon Lee ◽  
Min-Koo Han

AbstractA short channel polycrystalline silicon thin film transistor (poly-Si TFT), which has single grain boundary in the center of channel, is reported. The reported poly-Si TFT employs lateral grain growth method through aluminum patterns, which acts as a selective beam mask and a lateral heat sink during the laser irradiation, on an amorphous silicon layer. The electrical characteristics of the proposed poly-Si TFT have been considerably improved due to grain boundary density lowered. The reported short channel poly-Si TFT with single grain boundary exhibits high mobility as 222 cm2/Vsec and large on/off current ratio exceeding 1 × 108.


2007 ◽  
Vol 558-559 ◽  
pp. 851-856 ◽  
Author(s):  
Takahisa Yamamoto ◽  
Teruyasu Mizoguchi ◽  
S.Y. Choi ◽  
Yukio Sato ◽  
Naoya Shibata ◽  
...  

SrTiO3 bicrystals with various types of grain boundaries were prepared by joining two single crystals at high temperature. By using the bicrystals, we examined their current-voltage characteristics across single grain boundaries from a viewpoint of point defect segregation in the vicinity of the grain boundaries. Current-voltage property in SrTiO3 bicrystals was confirmed to show a cooling rate dependency from annealing temperature, indicating that cation vacancies accumulate due to grain boundary oxidation. The theoretical results obtained by ab-initio calculation clearly showed that the formation energy of Sr vacancies is the lowest comparing with Ti and O vacancies in oxidized atomosphere. The formation of a double Schottky barrier (DSB) in n-type SrTiO3 is considered to be closely related to the accumulation of the charged Sr vacancies. Meanwhile, by using three types of low angle boundaries, the excess charges related to one grain boundary dislocation par unit length was estimated. In this study, we summarized our results obtained in our group.


2013 ◽  
Vol 203-204 ◽  
pp. 427-430 ◽  
Author(s):  
Krzysztof Glowinski

Development of spatial microstructure imaging techniques (e.g. of automated serial sectioning) has made it possible to collect five macroscopic grain boundary parameters for sets of boundaries large enough for carrying out statistical studies. As a point of reference for future analysis of experimentally measured boundary data, various aspects of estimating the frequencies of occurrence of geometrically characteristic boundaries among random grain boundaries for the cases of cubic Oh, hexagonal D6h and tetragonal D4h point groups are discussed. Example frequencies, in particular for symmetric and improperly quasi-symmetric boundaries, are presented. Two approaches for verification whether a given boundary has a tilt or twist character are confronted, i.e. a method based on a distance function defined in the boundary parameter space and the widely known decomposition of a boundary into its tilt and twist components. The frequencies for tilt and twist boundaries calculated using both methods are compared.


2020 ◽  
Vol 20 (11) ◽  
pp. 6616-6621
Author(s):  
Hye Jin Mun ◽  
Min Su Cho ◽  
Jun Hyeok Jung ◽  
Won Douk Jang ◽  
Sang Ho Lee ◽  
...  

In this paper, we demonstrate the characteristics of a complementary metal-oxide-semiconductor (CMOS) logic inverter based on a polycrystalline-silicon (poly-Si) layer with a single grain boundary (GB). The proposed nanoscale CMOS logic inverter had been constructed on a poly-Si layer with a GB including four kind of traps at the center of the channel. The simulation variables are the acceptor-like deep trap (ADT), the donor-like deep trap (DDT), the acceptor-like shallow trap (AST) and the donor-like shallow trap (DST). The ADT and the DDT much stronger influences on the DC characteristics of the devices than the AST and the DST. The variation of voltage-transfer-curve (VTC) for CMOS devices directly affected the CMOS logic inverter with different traps.


1990 ◽  
Vol 170 (3-4) ◽  
pp. 315-318 ◽  
Author(s):  
R. Gross ◽  
P. Chaudhari ◽  
M. Kawasaki ◽  
M. Ketchen ◽  
A. Gupta

2000 ◽  
Vol 621 ◽  
Author(s):  
Ryoichi Ishihara

ABSTRACTThe offset of the underlying TiW is introduced in the island of Si, SiO2 and TiW on glass. During the dual-beam excimer-irradiation to the Si and the TiW, the offset in TiW acts as an extra heat source, which melts completely the Si film near the edge, whereas the Si inside is partially melted. The laterally columnar Si grains with a length of 3.2 μm were grown from the inside of the island towards the edge. By changing the shape of the edge, the direction of the solidification of the grain was successfully controlled in such a way that the all grain-boundaries are directed towards the edge and a single grain expands. The grain-boundary-free area as large as 4 μm × 3 μm was obtained at a predetermined position of glass.


2006 ◽  
Vol 73 (12) ◽  
Author(s):  
D. H. Hurley ◽  
O. B. Wright ◽  
O. Matsuda ◽  
T. Suzuki ◽  
S. Tamura ◽  
...  

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