As the electronics industry reaches the limits of lithographic processing at sub-10nm dimensions, alternate approaches to meet the demand for increasing device density, reducing package size and improving device performance are being explored. Die stacking approaches to reduce the path length between CPU, GPU and memory devices using a heterogeneous 3DIC chip stacking technology have recently been announced, while memory manufacturers have been creating HBM die stacks for use in servers and highspeed applications. At DuPont Electronics & Imaging (E&I), we have been working to enable 3DIC technology through the development of chemicals and processes such as CMP pads and slurries for polishing all the critical materials, chemical cleaners to remove residues, and photoresists to pattern TSVs, pads and pillars. In addition to these materials, E&I also provides permanent materials for hybrid bonding, including electrodeposited copper for TSVs, pads and pillars as well as tin-silver for pillar capping. Another critical part of hybrid bonding is the adhesive bonding material, which needs to be planarized and yet still have sufficient flow to bond at the same time as the Cu-Cu or Cu-SnAg interconnect. This paper will demonstrate how these critical materials can be used together to fabricate 3DIC devices using a conventional bonding tool. Processing of wafers with sub-20 micron pillars has been completed with good metal joining and void-free bonding of the BCB-based polymer adhesive.
Wall-lesion development in gaps: The role of the adhesive bonding material
