Effect of B dose and Ge preamorphization energy on the electrical and structural properties of ultrashallow junctions in silicon-on-insulator

MRS Proceedings ◽

10.1557/proc-0912-c01-10 ◽

2006 ◽

Vol 912 ◽

Cited By ~ 1

Author(s):

Justin J Hamilton ◽

Erik JH Collart ◽

Benjamin Colombeau ◽

Massimo Bersani ◽

Damiano Giubertoni ◽

...

Keyword(s):

Structural Properties ◽

Solid Phase ◽

Silicon Film ◽

Silicon On Insulator ◽

Bulk Silicon ◽

Defect Band ◽

Future Technology ◽

Ultrashallow Junctions ◽

P Type ◽

Technology Nodes

AbstractFormation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next generations of CMOS devices, particularly for source-drain extensions. For p-type dopant implants (boron), a promising method of increasing junction abruptness is to use Ge preamorphizing implants prior to ultra-low energy B implantation and solid-phase epitaxy regrowth to re-crystallize the amorphous Si. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Previous results have shown that the buried Si/SiO2 interface can improve dopant activation, but the effect depends on the detailed preamorphization conditions and further optimization is required. In this paper a range of B doses and Ge energies have been chosen in order to situate the end-of-range (EOR) defect band at various distances from the back interface of the active silicon film (the interface with the buried oxide), in order to explore and optimize further the effect of the interface on dopant behavior. Electrical and structural properties were measured by Hall Effect and SIMS techniques. The results show that the boron deactivates less in SOI material than in bulk silicon, and crucially, that the effect increases as the distance from the EOR defect band to the back interface is decreased. For the closest distances, an increase in junction steepness is also observed, even though the B is located close to the top surface, and thus far from the back interface. The position of the EOR defect band shows the strongest influence for lower B doses.

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Characterization of Buried-Nitride Silicon for Integrated Circuit Applications

MRS Proceedings ◽

10.1557/proc-93-113 ◽

1987 ◽

Vol 93 ◽

Cited By ~ 1

Author(s):

D. R. Myers ◽

H. J. Stein ◽

S. S. Tsao ◽

G. W. Arnold ◽

R. C. Hughes ◽

...

Keyword(s):

Silicon Nitride ◽

Transport Properties ◽

Integrated Circuit ◽

Silicon On Insulator ◽

Epitaxial Silicon ◽

Bulk Silicon ◽

Excess Silicon ◽

P Type ◽

Type Conduction

ABSTRACTWe have examined the microstructure and the transport properties of nitrogen-implanted silicon-on-insulator wafers, as well as the performance of integrated-circuit transistors fabricated in this material. The insulating regions were fabricated in silicon by the unpatterned implantation of 4×1017 /cm2, 300 keV nitrogen dimers followed by annealing at 1473 K for 5 hours. For these parameters, the buried nitrogen-implanted layer crystallized into α-silicon nitride, and contains ≈20% excess silicon in the form of silicon inclusions of 5–15 nm diameter. The surface silicon layers are characterized by low-mobility, p-type conduction. The buried dielectric has a resistivity of approximately 108 Ωcm. Functional p-channel, integrated circuit transistors have been fabricated in n-type epitaxial silicon grown over the buried-nitride wafers. These transistors devices are similar in performance to those fabricated in bulk silicon,(hole mobilities in inversion layers of 140 cm2/V-s), and demonstrate the suitability of the buried nitride process for integrated circuit applications.

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Modeling and Simulation of the Influence of SOI Structure on Damage Evolution and Ultra-shallow Junction Formed by Ge Preamorphization Implants and Solid Phase Epitaxial Regrowth

MRS Proceedings ◽

10.1557/proc-0912-c03-04 ◽

2006 ◽

Vol 912 ◽

Cited By ~ 5

Author(s):

Caroline Mok ◽

B. Colombeau ◽

M. Jaraiz ◽

P. Castrillo ◽

J. E. Rubio ◽

...

Keyword(s):

Damage Evolution ◽

Solid Phase ◽

Kinetic Monte Carlo ◽

Silicon On Insulator ◽

Bulk Silicon ◽

Shallow Junction ◽

Defect Interaction ◽

Epitaxial Regrowth ◽

Junction Formation ◽

Ultra Shallow Junctions

AbstractPreamorphization implant (PAI) prior to dopant implantation, followed by solid phase epitaxial regrowth (SPER) is of great interest due to its ability to form highly-activated ultra-shallow junctions. Coupled with growing interest in the use of silicon-on-insulator (SOI) wafers, modeling and simulating the influence of SOI structure on damage evolution and ultra-shallow junction formation is required. In this work, we use a kinetic Monte Carlo (kMC) simulator to model the different mechanisms involved in the process of ultra-shallow junction formation, including amorphization, recrystallization, defect interaction and evolution, as well as dopant-defect interaction in both bulk silicon and SOI. Simulation results of dopant concentration profiles and dopant activation are in good agreement with experimental data and can provide important insight for optimizing the process in bulk silicon and SOI.

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Solid-Phase Epitaxial Regrowth of Ion-Implanted Silicon on Sapphire Using Rapid Thermal Annealing

MRS Proceedings ◽

10.1557/proc-35-393 ◽

1984 ◽

Vol 35 ◽

Cited By ~ 3

Author(s):

A M Hodge ◽

A G Cullis ◽

N G Chew

Keyword(s):

Thermal Annealing ◽

Rapid Thermal Annealing ◽

Solid Phase ◽

Silicon Film ◽

Silicon On Insulator ◽

Full Potential ◽

Cross Sectional ◽

Epitaxial Regrowth ◽

Transmission Electron ◽

Device Processing

ABSTRACTSolid phase epitaxial regrowth of silicon on sapphire is used to improve the quality of as-received silicon films prior to conventional device processing. It has been shown that this is necessary, especially for layers of 0.3μm and thinner, if the full potential of this particular silicon on insulator technology is to be realised. Si+ ions are implanted at an energy and dose such that all but the surface of the silicon film is rendered amorphous. In this study, the layer is regrown using a rapid thermal annealer operated in the multi-second regime. A second shallower implant followed by rapid thermal annealing produces a further improvement. Characterisation of the material has been principally by cross-sectional transmission electron microscopy. The structures observed after different implant and regrowth treatments are discussed.

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p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

ECS Journal of Solid State Science and Technology ◽

10.1149/2162-8777/ac3bdf ◽

2021 ◽

Author(s):

Bharath Sreenivasulu Vakkalakula ◽

Narendar Vadthiya

Keyword(s):

High Performance ◽

Field Effect Transistors ◽

Oxide Semiconductor ◽

Power Performance ◽

Cmos Inverter ◽

Short Channel ◽

Future Technology ◽

Road Map ◽

P Type ◽

Technology Nodes

Abstract Silicon (Si) nanosheet (NS) metal-oxide semiconductor field effect transistors (MOSFETs) are realized as an outstanding structure to obtain better area scaling and power performance compared to FinFETs. Si NS MOSFETs provide high current drivability due to wider effective channel (Weff) and maintain better short channel performance. Here, the performance of junctionless (JL) NS p-MOSFET was evaluated by invoking HfxTi1-xO2 gate stack. The device performance was enhanced using various spacer dielectrics and the electrical characteristics are presented. Moreover, the effect of NS width variation on ION/IOFF, SS, Vth is presented and the analog/RF metrics of the device are evaluated. The power analysis of NS MOSFET is presented with respect to the ITRS road map. Our investigation reveals that the device exhibits an ION/IOFF ratio of more than ~106 with NS widths of 10 to 30 nm, respectively. For high-performance applications, the device exhibits better performance (ION) with higher NS widths. However, the threshold voltage downfall leads to deterioration in subthreshold performance with an increase in NS widths. With Si3N4 as a spacer dielectric the device exhibits better static power consumption for the CMOS inverter. By careful control of NS width and effective usage of spacer dielectric ensures better p-MOSFET design for future technology nodes.

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Cointegration of Gate-All-Around MOSFETs and Local Silicon-on-Insulator Optical Waveguides on Bulk Silicon

IEEE Transactions on Nanotechnology ◽

10.1109/tnano.2006.886748 ◽

2007 ◽

Vol 6 (1) ◽

pp. 118-125 ◽

Cited By ~ 8

Author(s):

K.E. Moselund ◽

D. Bouvet ◽

L. Tschuor ◽

V. Pott ◽

P. Dainesi ◽

...

Keyword(s):

Optical Waveguides ◽

Silicon On Insulator ◽

Bulk Silicon

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Effects of thin SiO2capping layer on silicon‐on‐insulator formation by lateral solid‐phase epitaxy

Applied Physics Letters ◽

10.1063/1.107381 ◽

1992 ◽

Vol 60 (1) ◽

pp. 80-81 ◽

Cited By ~ 3

Author(s):

K. Kusukawa ◽

M. Ohkura ◽

M. Moniwa ◽

M. Miyao

Keyword(s):

Solid Phase ◽

Silicon On Insulator ◽

Solid Phase Epitaxy

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Enhancement of Breakdown Voltage in SOI MOSFET Using Buried p-Type Silicon

10.21203/rs.3.rs-621286/v1 ◽

2021 ◽

Author(s):

Deivakani M ◽

Sumithra M.G ◽

Anitha P ◽

Jenopaul P ◽

Priyesh P. Gandhi ◽

...

Keyword(s):

Breakdown Voltage ◽

Impact Ionization ◽

Semiconductor Industry ◽

Silicon Layer ◽

Silicon On Insulator ◽

Physical Models ◽

Oxide Semiconductor ◽

Soi Mosfet ◽

P Type ◽

Conventional Device

Abstract Semiconductor industry is still looking for the enhancement of breakdown voltage in Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Thus, in this paper, heavy n-type doping below the channel is proposed for SOI MOSFET. Simulation of SOI MOSFET is carried out using 2D TCAD physical simulator. In the conventional device, with no p-type doping is used at the bottom silicon layer. While, in proposed device, p-type doping of 1×1018 cm-3 is used. Physical models are used in the simulation to achieve realistic performance. The models are mobility model, impact ionization model and ohmic contact model. Using TCAD simulation, electron/hole current density, impact generation, recombination and breakdown phenomena are analyzed. It is found that the proposed with p-type doping of 1×1018 cm-3 for SOI MOSFET yields high breakdown voltage. In contrast to conventional device, 20% improvement in breakdown voltage is achieved for proposed device.

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Applicability of Phosphorus and Boron Diffusion Parameters Extracted from Predeposition to Drive-in Diffusion for Bulk Silicon and Silicon-on-Insulator

Japanese Journal of Applied Physics ◽

10.1143/jjap.42.1503 ◽

2003 ◽

Vol 42 (Part 1, No. 4A) ◽

pp. 1503-1510 ◽

Cited By ~ 4

Author(s):

Eisuke Arai ◽

Daisuke Iida ◽

Hiroshi Asai ◽

Yasushi Ieki ◽

Hideo Uchida ◽

...

Keyword(s):

Silicon On Insulator ◽

Boron Diffusion ◽

Bulk Silicon ◽

Diffusion Parameters

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Measurement of Copper in p-Type Silicon Using Charge-Carrier Lifetime Methods

Solid State Phenomena ◽

10.4028/www.scientific.net/ssp.108-109.643 ◽

2005 ◽

Vol 108-109 ◽

pp. 643-648 ◽

Cited By ~ 3

Author(s):

Marko Yli-Koski ◽

Hele Savin ◽

E. Saarnilehto ◽

Antti Haarahiltunen ◽

Juha Sinkkonen ◽

...

Keyword(s):

Charge Carrier ◽

Room Temperature ◽

Carrier Lifetime ◽

Detection Sensitivity ◽

Bulk Silicon ◽

Recombination Activity ◽

P Type ◽

Copper Detection ◽

Charge Carrier Lifetime

We compare SPV technique with µ−PCD for the determination of recombination activity of copper precipitates in p-Si. The copper precipitates were formed in bulk silicon through illumination at room temperature. We observed that the recombination activities of copper precipitates measured with SPV are higher than the ones measured with µ−PCD technique. However, it seems that the copper detection sensitivity is about the same with SPV and µ−PCD techniques.

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