Effective mass approximation versus full atomistic model to calculate the output characteristics of a gate-all-around germanium nanowire field effect transistor (GAA-GeNW-FET)

2018 ◽  
Vol 113 ◽  
pp. 769-776 ◽  
Author(s):  
Amir Hossein Bayani ◽  
Jan Voves ◽  
Daryoosh Dideban
2006 ◽  
Vol 913 ◽  
Author(s):  
Pei W. Ding ◽  
Kristel Fobelets ◽  
Jesus E Velazquez-Perez

AbstractA novel field effect transistor (FET) that uses 3-dimensional (3-D) embedded gate fingers – the Screen-Grid Field Effect Transistor (SGFET) – is proposed. The gating action of the SGFET is based on the design of multiple gating cylinders into the channel region, perpendicular to the current flow. Such configuration allows a full 3-D gate control of the current which improves the device characteristics by increasing the gate to channel coupling. Initial investigations of the SGFET using 3-D TCAD TaurusTM simulation software are presented in this paper. The results indicate that the proposed SGFET offers the possibility of downscaling without degrading the output characteristics. A comparison between the SGFET and both bulk and SOI MOSFETs shows the superior characteristics of the SGFET for low power operation.


2021 ◽  
Author(s):  
Shaiful Bakhtiar Hashim ◽  
Zurita Zulkifli ◽  
Sukreen Hana Herman

Abstract A SPICE model for extended-gate field-effect transistor (EGFET) based pH sensor was developed using standard discrete components. Capacitors and resistors were used to represent the sensing and reference electrodes in the EGFET sensor system and the values of the discrete component were varied to see the output of the transistor. These variations were done to emulate the EGFET sensor output in different pH values. It was found that the experimental transfer and output characteristics of the EGFET were very similar to those from the SPICE simulation. Other than that, the changes of value components in the equivalent circuit did not affect the transfer and output characteristics graph, but the capacitor value produced significant output variation in the simulation. This can be related to the modification on the equivalent circuit was done with additional voltage, VSB (source to bulk) to produce the different VT values at different pH.


2018 ◽  
Vol 924 ◽  
pp. 949-952 ◽  
Author(s):  
David J. Spry ◽  
Philip G. Neudeck ◽  
Dorothy Lukco ◽  
Liang Yu Chen ◽  
Michael J. Krasowski ◽  
...  

This report describes more than 5000 hours of successful 500 °C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 °C. After 100 hours of 500 °C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 °C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 °C in comparison to what is observed for Earth-atmosphere oven testing at 500 °C.


2000 ◽  
Vol 87 (10) ◽  
pp. 7466-7475 ◽  
Author(s):  
Z. S. Gribnikov ◽  
N. Z. Vagidov ◽  
A. N. Korshak ◽  
V. V. Mitin

2021 ◽  
pp. 255-259
Author(s):  
Chaorun Pu ◽  
Qiuhong Tan ◽  
Chao Zhang ◽  
Li Ren ◽  
Xia Zhang ◽  
...  

2009 ◽  
Vol 23 (19) ◽  
pp. 3871-3880 ◽  
Author(s):  
RAHIM FAEZ ◽  
SEYED EBRAHIM HOSSEINI

A carbon nanotube field effect transistor (CNTFET) has been studied based on the Schrödinger–Poisson formalism. To improve the saturation range in the output characteristics, new structures for CNTFETs are proposed. These structures are simulated and compared with the conventional structure. Simulations show that these structures have a wider output saturation range. With this, larger drain-source voltage (Vds) can be used, which results in higher output power. In the digital circuits, higher Vds increases noise immunity.


2011 ◽  
Vol 679-680 ◽  
pp. 657-661 ◽  
Author(s):  
Kevin M. Speer ◽  
Philip G. Neudeck ◽  
Mehran Mehregany

We introduce the vacuum field-effect transistor (VacFET), the first SiC FET to use a vacuum-sealed cavity in place of the traditional, solid gate dielectric. This device architecture eliminates the need to thermally oxidize the SiC surface, a practice which has been widely reported to inhibit the performance and reliability of SiC MOSFETs. Using a combination of batch-compatible electronics and micromachining processing techniques, a polycrystalline SiC bridge is suspended above a 4H-SiC substrate, and the underlying cavity is sealed under vacuum. The fundamental studies made possible by such a device could shed much-needed light on the basic electronic properties of an inverted SiC surface. In this introductory report, we detail the analytical design and fabrication necessary to manufacture the VacFET, and we also demonstrate proof of the concept using turn-on and output characteristics of the first functional SiC device.


2021 ◽  
Author(s):  
Sweta Chander ◽  
Sanjeet Kumar Sinha ◽  
Prince Kumar Singh ◽  
Ashish Kumar Singh

Abstract This paper presents a numerically simulated Ge-source based Tunnel Field Effect Transistor with (TFETs) SiO 2 segregation between the channel and drain. The developed device has been compared with conventional TFET and without isolated heterojunction TFET. The use of oxide segregation between channel and drain enhances the performance of the device in terms of ON-state current as well as subthreshold swing (SS). The electrical characteristics such as surface potential, electric field, transfer characteristics, output characteristics of the proposed device have been studied. The temperature variation of the proposed device has also been studied. The proposed device offers high ON current of 3x10 4 A, I ON /I OFF ratio of ~10 11, and enhanced SS of 30 mV/dec. The validity of the proposed device has been done by Synopsys Sentaurus TCAD.


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