Organic FETs with HWCVD silicon nitride as a passivation layer and gate dielectric

AbstractTo extend the scaling limit of thermal SiO2, in the ultra thin regime when the direct tunneling current becomes significant, members of our group embarked on a program to explore the potential of silicon nitride as an alternative gate dielectric. Silicon nitride can be deposited using several CVD methods and its properties significantly depend on the method of deposition. Although these CVD methods can give good physical properties, the electrical properties of devices made with CVD silicon nitride show very poor performance related to very poor interface, poor stability, presence of large quantity of bulk traps and high gate leakage current. We have employed the rather newly developed Hot Wire Chemical Vapor Deposition (HWCVD) technique to develop the a:SiN:H material. From the results of large number of optimization experiments we propose the atomic hydrogen of the substrate surface prior to deposition to improve the quality of gate dielectric. Our preliminary results of these efforts show a five times improvement in the fixed charges and interface state density.

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Studies on a Novel Qualification Method of Silicon Nitride Layer

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0186 ◽

2016 ◽

Author(s):

Younan Hua ◽

Bingsheng Khoo ◽

Henry Leong ◽

Yixin Chen ◽

Eason Chan ◽

...

Keyword(s):

Silicon Nitride ◽

Silicon Substrate ◽

Nitride Layer ◽

Passivation Layer ◽

Wafer Fabrication ◽

Wafer Surface ◽

Si3n4 Layer ◽

Silicon Nitride Layer ◽

Passivation Layers ◽

Pinhole Test

Abstract In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.

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Effect of Ultrathin Si Passivation Layer for Ge MOS Structure with La2O3 Gate Dielectric

ECS Meeting Abstracts ◽

10.1149/ma2008-02/25/1945 ◽

2008 ◽

Keyword(s):

Gate Dielectric ◽

Passivation Layer ◽

Mos Structure

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Improved interfacial and electrical properties of HfLaON gate dielectric Ge MOS capacitor by NbON/Si dual passivation layer and fluorine incorporation

Applied Physics Letters ◽

10.1063/1.4967186 ◽

2016 ◽

Vol 109 (19) ◽

pp. 193504 ◽

Cited By ~ 6

Author(s):

Yong Huang ◽

Jing-Ping Xu ◽

Lu Liu ◽

Pui-To Lai ◽

Wing-Man Tang

Keyword(s):

Electrical Properties ◽

Gate Dielectric ◽

Passivation Layer ◽

Mos Capacitor

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High-permitivity cerium oxide prepared by molecular beam deposition as gate dielectric and passivation layer and applied to AlGaN/GaN power high electron mobility transistor devices

Japanese Journal of Applied Physics ◽

10.7567/jjap.55.051001 ◽

2016 ◽

Vol 55 (5) ◽

pp. 051001 ◽

Cited By ~ 2

Author(s):

Yu Sheng Chiu ◽

Jen Ting Liao ◽

Yueh Chin Lin ◽

Shin Chien Liu ◽

Tai Ming Lin ◽

...

Keyword(s):

Cerium Oxide ◽

Electron Mobility ◽

Molecular Beam ◽

Gate Dielectric ◽

High Electron Mobility Transistor ◽

Passivation Layer ◽

High Electron ◽

High Electron Mobility ◽

Molecular Beam Deposition ◽

Beam Deposition

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Reactive Sputtered Silicon Nitride as an Alternative Passivation Layer for Microelectrode Arrays in Sensitive Bioimpedimetric Cell Monitoring

ACS Applied Materials & Interfaces ◽

10.1021/acsami.1c14981 ◽

2021 ◽

Author(s):

Sabine Schmidt ◽

Tobias Haensch ◽

Ronny Frank ◽

Heinz-Georg Jahnke ◽

Andrea A. Robitzki

Keyword(s):

Silicon Nitride ◽

Microelectrode Arrays ◽

Passivation Layer ◽

Cell Monitoring

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Hydrogenated amorphous silicon nitride (a-SiNx:H) as surface passivation layer

Surface Passivation of Industrial Crystalline Silicon Solar Cells ◽

10.1049/pbpo106e_ch11 ◽

2018 ◽

pp. 179-195

Author(s):

Machteld Lamers ◽

Arthur Weeber

Keyword(s):

Silicon Nitride ◽

Amorphous Silicon ◽

Surface Passivation ◽

Hydrogenated Amorphous Silicon ◽

Passivation Layer ◽

Amorphous Silicon Nitride ◽

Hydrogenated Amorphous

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Silicon Nitride as Top Gate Dielectric for Epitaxial Graphene

Materials Science Forum ◽

10.4028/www.scientific.net/msf.740-742.149 ◽

2013 ◽

Vol 740-742 ◽

pp. 149-152 ◽

Cited By ~ 1

Author(s):

Peter Wehrfritz ◽

Felix Fromm ◽

Stefan Malzer ◽

Thomas Seyller

Keyword(s):

Silicon Nitride ◽

Photoelectron Spectroscopy ◽

Gate Dielectric ◽

Chemical Vapor ◽

Epitaxial Graphene ◽

Plasma Process ◽

Voltage Range ◽

Before And After ◽

Field Effect Devices ◽

A Minor

Silicon nitride (SiN) was deposited by plasma enhanced chemical vapor deposition (PECVD) as a top gate dielectric on epitaxial graphene on 6H-SiC(0001). We compare x-ray photoelectron spectroscopy (XPS), Raman spectroscopy, and transport measurements which were performed before and after the SiN deposition. We demonstrate that closed layers of SiN are formed without the need for surface activation and that the plasma process leads only to a minor degradation of the graphene. The SiN layer induces strong n-type doping. For a limited gate voltage range, a small hysteresis of 0.2 V is observed in top-gated field effect devices.

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