State creation induced by gate bias stress in unhydrogenated polysilicon TFTs

1999 ◽  
Vol 337 (1-2) ◽  
pp. 101-104 ◽  
Author(s):  
B. Tala-Ighil ◽  
A. Rahal ◽  
K. Mourgues ◽  
A. Toutah ◽  
L. Pichon ◽  
...  
2003 ◽  
Vol 427 (1-2) ◽  
pp. 340-344
Author(s):  
H. Toutah ◽  
J.F. Llibre ◽  
B. Tala-Ighil ◽  
B. Boudart ◽  
T. Mohammed-Brahim

2018 ◽  
Vol 49 ◽  
pp. 597-600
Author(s):  
Xiaoliang Zhou ◽  
Xiaodong Zhang ◽  
Yang Shao ◽  
Letao Zhang ◽  
Hongyu He ◽  
...  

2011 ◽  
Vol 99 (2) ◽  
pp. 022104 ◽  
Author(s):  
Te-Chih Chen ◽  
Ting-Chang Chang ◽  
Tien-Yu Hsieh ◽  
Wei-Siang Lu ◽  
Fu-Yen Jian ◽  
...  

2017 ◽  
Vol 32 (2) ◽  
pp. 91-96
Author(s):  
张猛 ZHANG Meng ◽  
夏之荷 XIA Zhi-he ◽  
周玮 ZHOU Wei ◽  
陈荣盛 CHEN Rong-sheng ◽  
王文 WONG Man ◽  
...  

2015 ◽  
Vol 54 (4) ◽  
pp. 044101 ◽  
Author(s):  
Fei Sang ◽  
Maojun Wang ◽  
Chuan Zhang ◽  
Ming Tao ◽  
Bing Xie ◽  
...  

Energies ◽  
2020 ◽  
Vol 13 (10) ◽  
pp. 2628 ◽  
Author(s):  
Surya Elangovan ◽  
Stone Cheng ◽  
Edward Yi Chang

We present a detailed study of dynamic switching instability and static reliability of a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High-Electron-Mobility-Transistor (MIS-HEMT) based cascode switch under off-state (negative bias) Gate bias stress (VGS, OFF). We have investigated drain channel current (IDS, Max) collapse/degradation and turn-on and rise-time (tR) delay, on-state resistance (RDS-ON) and maximum transconductance (Gm, max) degradation and threshold voltage (VTH) shift for pulsed and prolonged off-state gate bias stress VGS, OFF. We have found that as stress voltage magnitude and stress duration increases, similarly IDS, Max and RDS-ON degradation, VTH shift and turn-on/rise time (tR) delay, and Gm, max degradation increases. In a pulsed off-state VGS, OFF stress experiment, the device instabilities and degradation with electron trapping effects are studied through two regimes of stress voltages. Under low stress, VTH shift, IDS collapse, RDS-ON degradation has very minimal changes, which is a result of a recoverable surface state trapping effect. For high-stress voltages, there is an increased and permanent VTH shift and high IDS, Max and RDS-ON degradation in pulsed VGS, Stress and increased rise-time and turn-on delay. In addition to this, a positive VTH shift and Gm, max degradation were observed in prolonged stress experiments for selected high-stress voltages, which is consistent with interface state generation. These findings provide a path to understand the failure mechanisms under room temperature and also to accelerate the developments of emerging GaN cascode technologies.


2019 ◽  
Vol 8 (7) ◽  
pp. Q3034-Q3040 ◽  
Author(s):  
Yen-Chi Cheng ◽  
Sheng-Po Chang ◽  
Shoou-Jinn Chang ◽  
Tien-Hung Cheng ◽  
Yen-Lin Tsai ◽  
...  

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