P-6.1: Asymmetric Effects of Gate-Bias Stress Voltage on the Stability under Positive and Negative Gate-Bias Stress of a-IGZO TFTs

2018 ◽  
Vol 49 ◽  
pp. 597-600
Author(s):  
Xiaoliang Zhou ◽  
Xiaodong Zhang ◽  
Yang Shao ◽  
Letao Zhang ◽  
Hongyu He ◽  
...  
Keyword(s):  
Gate Bias ◽  
Asymmetric Effects ◽  
Bias Stress ◽  
The Stability ◽  
Stress Voltage ◽  
Gate Bias Stress

scholarly journals Influence of the gate bias stress on the stability of n-type organic field-effect transistors based on dicyanovinylene–dihydroindenofluorene semiconductors

2018 ◽  
Vol 2 (9) ◽  
pp. 1631-1641 ◽  
Author(s):  
S. Bebiche ◽  
P. A. Cisneros-Perez ◽  
T. Mohammed-Brahim ◽  
M. Harnois ◽  
J. Rault-Berthelot ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Gate Bias ◽  
Organic Field Effect Transistors ◽  
Bias Stress ◽  
The Stability ◽  
Gate Bias Stress

The electrical stabilities of n-type Organic Field-Effect Transistors (OFETs) based on dihydroindeno[1,2-b]fluorene and dihydroindeno[2,1-b]fluorene derivatives have been studied.

Study of the stability of polycrystalline silicon by means of the behavior of thin film transistors under gate bias stress

2002 ◽  
Vol 299-302 ◽  
pp. 497-501 ◽  
Author(s):  
T. Mohammed-Brahim ◽  
A. Rahal ◽  
G. Gautier ◽  
F. Raoult ◽  
H. Toutah ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Gate Bias ◽  
Bias Stress ◽  
The Stability ◽  
Gate Bias Stress

Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor

2011 ◽  
Vol 99 (2) ◽  
pp. 022104 ◽  
Author(s):  
Te-Chih Chen ◽  
Ting-Chang Chang ◽  
Tien-Yu Hsieh ◽  
Wei-Siang Lu ◽  
Fu-Yen Jian ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Charge Trapping ◽  
Gate Bias ◽  
Degradation Behavior ◽  
Bias Stress ◽  
Trapping Effect ◽  
Gate Bias Stress

Degradation behavior and degradation mechanism of bridged-grain polycrystalline silicon thin film transistors under AC gate bias stress

2017 ◽  
Vol 32 (2) ◽  
pp. 91-96
Author(s):  
张猛 ZHANG Meng ◽  
夏之荷 XIA Zhi-he ◽  
周玮 ZHOU Wei ◽  
陈荣盛 CHEN Rong-sheng ◽  
王文 WONG Man ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Degradation Mechanism ◽  
Gate Bias ◽  
Degradation Behavior ◽  
Silicon Thin Film ◽  
Bias Stress ◽  
Gate Bias Stress

Investigation of the threshold voltage drift in enhancement mode GaN MOSFET under negative gate bias stress

2015 ◽  
Vol 54 (4) ◽  
pp. 044101 ◽  
Author(s):  
Fei Sang ◽  
Maojun Wang ◽  
Chuan Zhang ◽  
Ming Tao ◽  
Bing Xie ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Bias ◽  
Bias Stress ◽  
Enhancement Mode ◽  
Voltage Drift ◽  
Gate Bias Stress

scholarly journals Reliability Characterization of Gallium Nitride MIS-HEMT Based Cascode Devices for Power Electronic Applications

Energies ◽  
2020 ◽  
Vol 13 (10) ◽  
pp. 2628 ◽  
Author(s):  
Surya Elangovan ◽  
Stone Cheng ◽  
Edward Yi Chang
Keyword(s):  
Gallium Nitride ◽  
Rise Time ◽  
High Stress ◽  
High Electron Mobility Transistor ◽  
Interface State ◽  
High Electron ◽  
Gate Bias ◽  
Bias Stress ◽  
Turn On ◽  
Gate Bias Stress

We present a detailed study of dynamic switching instability and static reliability of a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High-Electron-Mobility-Transistor (MIS-HEMT) based cascode switch under off-state (negative bias) Gate bias stress (VGS, OFF). We have investigated drain channel current (IDS, Max) collapse/degradation and turn-on and rise-time (tR) delay, on-state resistance (RDS-ON) and maximum transconductance (Gm, max) degradation and threshold voltage (VTH) shift for pulsed and prolonged off-state gate bias stress VGS, OFF. We have found that as stress voltage magnitude and stress duration increases, similarly IDS, Max and RDS-ON degradation, VTH shift and turn-on/rise time (tR) delay, and Gm, max degradation increases. In a pulsed off-state VGS, OFF stress experiment, the device instabilities and degradation with electron trapping effects are studied through two regimes of stress voltages. Under low stress, VTH shift, IDS collapse, RDS-ON degradation has very minimal changes, which is a result of a recoverable surface state trapping effect. For high-stress voltages, there is an increased and permanent VTH shift and high IDS, Max and RDS-ON degradation in pulsed VGS, Stress and increased rise-time and turn-on delay. In addition to this, a positive VTH shift and Gm, max degradation were observed in prolonged stress experiments for selected high-stress voltages, which is consistent with interface state generation. These findings provide a path to understand the failure mechanisms under room temperature and also to accelerate the developments of emerging GaN cascode technologies.

Stability Improvement of Nitrogen Doping on IGO TFTs under Positive Gate Bias Stress and Hysteresis Test

2019 ◽  
Vol 8 (7) ◽  
pp. Q3034-Q3040 ◽  
Author(s):  
Yen-Chi Cheng ◽  
Sheng-Po Chang ◽  
Shoou-Jinn Chang ◽  
Tien-Hung Cheng ◽  
Yen-Lin Tsai ◽  
...  
Keyword(s):  
Nitrogen Doping ◽  
Gate Bias ◽  
Bias Stress ◽  
Gate Bias Stress
Sign in / Sign up

Export Citation Format

Share Document