Incendiary characteristics of electrostatic discharge for dust and gas explosion

2001 ◽  
Vol 14 (6) ◽  
pp. 547-551 ◽  
Author(s):  
M. Nifuku ◽  
H. Katoh
Keyword(s):  
Electrostatic Discharge ◽  
Gas Explosion

The Research and Implementation of Electrostatic Detonating Gas Simulation Experiment System Controller Based on Nios II

2011 ◽  
Vol 219-220 ◽  
pp. 750-753
Author(s):  
Xiu Jie Dong ◽  
Sheng Jie Ma ◽  
Qi Xiao Sun ◽  
Liang Zhang
Keyword(s):  
Human Body ◽  
Simulation Experiment ◽  
Electrostatic Discharge ◽  
Gas Explosion ◽  
Experiment System ◽  
Gas Concentration ◽  
Nios Ii ◽  
Series Of Experiments ◽  
System Controller ◽  
Detonating Gas

The electrostatic discharge detonating gas simulation experiment system based on Nios II is developed in this paper.This system uses flexible and highly efficient SOPC technology,which embeds many functional modules.The system can simulate the mine gas environment, measure the oxygen, temperature and the gas concentration that most likely detonating gas, and real-time display in the LED screen, so as to obtain important data of gas explosion in coal environmental, which provide theoretical and experimental basis for farmulating standards of electrostatic security of human body and the safety of production in coal mine. It can conduct a series of experiments about electrostatic discharge of human body detonating gas mixture.

Electric Shock and Safety Evaluation for Electrostatic Discharge from Human

2017 ◽  
Vol 137 (4) ◽  
pp. 229-235
Author(s):  
Yoshinori Taka ◽  
Akimasa Hirata ◽  
Kenichi Yamazaki ◽  
Osamu Fujiwara
Keyword(s):  
Electric Shock ◽  
Electrostatic Discharge ◽  
Safety Evaluation

Conversion of a D-Mode FET to an E-Mode FET via Electrostatic Discharge in a GaAs Power Amplifier Duplexer Module

2013 ◽  
Author(s):  
Rose Emergo ◽  
Steve Brockett
Keyword(s):  
Cross Section ◽  
Power Amplifier ◽  
Electrostatic Discharge ◽  
Fault Isolation ◽  
Design Change ◽  
Eds Analysis ◽  
Defect Simulation

Abstract This paper outlines the systematic isolation of an electrostatic discharge defect on a depletion-mode FET. Topics covered are fault isolation, FIB-STEM cross-section and EDS analysis, and defect simulation. Multiple GaAs PA devices were submitted for analysis after failing different reliability stresses. Fault isolation revealed ESD damage on a DFET connected to the VMODE0 pin. Simulation of the failure showed that, most likely, the defect was caused by CDM stress. A design change of inserting a resistor between the VMODE0 pin and the DFET made the device more robust against CDM stress.

A Methodology for Characterizing System-Level ESD Sensitivity

2004 ◽  
Author(s):  
Marie-Pascale Chagny ◽  
John A. Naoum
Keyword(s):  
Electrostatic Discharge ◽  
Computer Systems ◽  
Electronic Equipment ◽  
Experimental Methodology ◽  
Computer Users ◽  
System Level ◽  
Permanent Damage ◽  
Design Improvement ◽  
Desktop Computers

Abstract Over the years, failures induced by an electrostatic discharge (ESD) have become a major concern for semiconductor manufacturers and electronic equipment makers. The ESD events that cause destructive failures have been studied extensively [1, 2]. However, not all ESD events cause permanent damage. Some events lead to recoverable failures that disrupt system functionality only temporarily (e.g. reboot, lockup, and loss of data). These recoverable failures are not as well understood as the ones causing permanent damage and tend to be ignored in the ESD literature [3, 4]. This paper analyzes and characterizes how these recoverable failures affect computer systems. An experimental methodology is developed to characterize the sensitivity of motherboards to ESD by simulating the systemlevel ESD events induced by computer users. The manuscript presents a case study where this methodology was used to evaluate the robustness of desktop computers to ESD. The method helped isolate several weak nets contributing to the failures and identified a design improvement. The result was that the robustness of the systems improved by a factor of 2.

Characterization of CMOS Structures (0.6 µm process) Submitted to HBM and COM ESD Stress Tests

1997 ◽  
Author(s):  
G. Meneghesso ◽  
E. Zanoni ◽  
P. Colombo ◽  
M. Brambilla ◽  
R. Annunziata ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Electrostatic Discharge ◽  
Stress Test ◽  
Complete Characterization ◽  
Stress Tests ◽  
Test Procedures ◽  
Emission Microscopy ◽  
Fast Rise ◽  
Scanning Electron

Abstract In this work, we present new results concerning electrostatic discharge (ESD) robustness of 0.6 μm CMOS structures. Devices have been tested according to both HBM and socketed CDM (sCDM) ESD test procedures. Test structures have been submitted to a complete characterization consisting in: 1) measurement of the tum-on time of the protection structures submitted to pulses with very fast rise times; 2) ESD stress test with the HBM and sCDM models; 3) failure analysis based on emission microscopy (EMMI) and Scanning Electron Microscopy (SEM).

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