A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio

This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.

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Metamodelling Techniques for the Optimal Design of Low-Noise Amplifiers

Electronics ◽

10.3390/electronics9050787 ◽

2020 ◽

Vol 9 (5) ◽

pp. 787

Author(s):

Amel Garbaya ◽

Mouna Kotti ◽

Mourad Fakhfakh ◽

Esteban Tlelo-Cuautle

Keyword(s):

Particle Swarm Optimization ◽

Optimal Design ◽

Noise Figure ◽

Low Noise ◽

Low Noise Amplifiers ◽

Scattering Parameters ◽

Perfect Agreement ◽

Swarm Optimization ◽

The Third ◽

Intercept Point

In this article we deal with the optimal sizing of low-noise amplifiers (LNAs) using newly proposed metamodeling techniques. The main objective is to construct metamodels of main performances of the LNAs (namely, the third intercept point (IIP3), the scattering parameters (Sij), and the noise figure (NF)) and use them inside an optimization kernel for maximizing the circuits’ performances. The kriging surrogate modelling technique is used for constructing these models. The particle swarm optimization (PSO) technique is considered as the optimization metaheuristic. Two CMOS amplifiers are considered: a UMTS LNA and a multistandard LNA. Obtained results show that, at the considered working frequencies, the first LNA exhibits at 2.14 GHz a noise figure of 1.30 dB, an S21 of 16.01 dB, an S11 of −12.60 dB, and an IIP3 of 8.30 dBm. At 2 GHz, the second LNA has a noise figure of 1.24 dB, an S21 of 17.16 dB, an S11 of −13.74 dB, and an IIP3 of 4.30 dBm. Comparisons between results obtained using the constructed models and those of the simulation are presented to show the perfect agreement between them.

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Plug-and-play transceiver with high gain and ultra low noise figure for IEEE 802.15.4 application

Facta universitatis - series Electronics and Energetics ◽

10.2298/fuee1902231l ◽

2019 ◽

Vol 32 (2) ◽

pp. 231-238

Author(s):

Josue Lopez-Leyva ◽

Miguel Ponce-Camacho ◽

Ariana Talamantes-Alvarez

Keyword(s):

High Speed ◽

Ieee 802.15.4 ◽

Noise Figure ◽

Impedance Matching ◽

High Gain ◽

Low Noise ◽

Scattering Parameters ◽

Performance Simulation ◽

Noise Amplifier ◽

And Performance

This paper shows the design and performance simulation of a 2.4 GHz plugand- play transceiver based on a high speed switch for IEEE 802.15.4 applications. The electrical design was optimized taking into account the scattering parameters, inputoutput impedance matching and minimum trace width. The simulation results show an important performance regarding the Noise Figure (0.38 dB) and gain (21 dB) at particular temperature for reception mode, transmission scattering parameters (S12 and S21) and reflection scattering parameters (all the rest parameters) for both mode operation (Power Amplifier and Low Noise Amplifier).

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RECENT ADVANCES AND DESIGN TRENDS IN CMOS RADIO FREQUENCY INTEGRATED CIRCUITS

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156405003247 ◽

2005 ◽

Vol 15 (02) ◽

pp. 377-428

Author(s):

DAVID J. ALLSTOT ◽

SANKARAN ANIRUDDHAN ◽

MIN CHU ◽

JEYANANDH PARAMESH ◽

SUDIP SHEKHAR

Keyword(s):

Integrated Circuits ◽

Phase Noise ◽

Noise Figure ◽

Building Blocks ◽

Intermediate Frequency ◽

Direct Conversion ◽

Low Noise ◽

Low Noise Amplifiers ◽

Common Source ◽

Lower Phase

Several state-of-the-art wireless receiver architectures are presented including the traditional super-heterodyne, the image-reject heterodyne, the direct-conversion, and the very-low intermediate frequency (VLIF). The case studies are followed by a detailed view of receiver building blocks: low-noise amplifiers (LNA), mixers, and voltage-controlled oscillators (VCO). Two popular topologies currently exist for LNAs: the common-gate configuration, which offers low power consumption with superior stability, robustness and linearity performance, and its common-source counterpart, which provides comparatively higher gain and lower noise figure. Aside from the traditional passive and active Gilbert mixers, the even-harmonic and masking-quadrature mixers are developed to combat second-order non-linearity and improve image-rejection, respectively. For quadrature carrier generation, the degeneration-injected QVCO is superior to the cascode-injected QVCO both in terms of phase noise and tuning range. The Colpitts QVCO is attractive as a low-noise alternative as it does not disturb the output voltage as much as its traditional LC counterpart and thus offers lower phase noise.

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RF and Microwave Test of MMICs from Qualification to Mass Production

Advances in Monolithic Microwave Integrated Circuits for Wireless Systems ◽

10.4018/978-1-60566-886-4.ch011 ◽

2012 ◽

pp. 333-345

Author(s):

Mohamed Mabrouk

Keyword(s):

Integrated Circuits ◽

Noise Figure ◽

High Volume ◽

Low Noise ◽

Production Environment ◽

Rf Receiver ◽

High Volume Production ◽

Volume Production ◽

Noise Amplifier ◽

Insertion Losses

This chapter describes some basic characteristic responses that must be known for each Monolithic Microwave Integrated Circuits. The main parameters such Return Loss, Insertion Losses or Gain, Power at 1dB compression, InterModulation Products or Noise Figure are very important and have to be measured before using the device in final applications. Basic rules of Test and Measurement in RF and Microwaves, as well for characterization on benches as for high volume production using Automatic Test Equipments installed in test platforms, are summarized for helping today’s test engineers to develop their own test solutions. The device, that was characterized on bench and tested in production environment, is a monolithic, integrated low noise amplifier (LNA) and mixer usable in RF receiver Front-End applications for Personal Communications functioning on frequency wideband between 0.1 and 2.0 GHz.

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Design of Broadband W-Band Waveguide Package and Application to Low Noise Amplifier Module

Electronics ◽

10.3390/electronics8050523 ◽

2019 ◽

Vol 8 (5) ◽

pp. 523 ◽

Cited By ~ 4

Author(s):

Jihoon Doo ◽

Woojin Park ◽

Wonseok Choe ◽

Jinho Jeong

Keyword(s):

Integrated Circuits ◽

Insertion Loss ◽

Noise Figure ◽

Space Structure ◽

Low Noise ◽

Low Noise Amplifier ◽

Waveguide Section ◽

External Bias ◽

W Band ◽

Noise Amplifier

In this paper, the broadband millimeter-wave waveguide package, which can cover the entire W-band (75–110 GHz) is presented and applied to build a low noise amplifier module. For this purpose, a broadband waveguide-to-microstrip transition was designed using an extended E-plane probe in a low-loss and thin dielectric substrate. The end of the probe substrate was firmly fixed on to the waveguide wall in order to minimize the performance degradation caused by the probable bending of the substrate. In addition, we predicted and analyzed in-band resonances by the simulations that are caused by the empty spaces in the waveguide package to accommodate integrated circuits (ICs) and external bias circuits. These resonances are removed by designing an asymmetrical bias space structure with a radiation boundary at an external bias connection plane. The bond-wires, which are used to connect the ICs with the transition, can generate impedance mismatches and limit the bandwidth performance of the waveguide package. Their effect is carefully compensated for by designing the broadband two-section matching circuits in the transition substrate. Finally, the broadband waveguide package is designed using a commercial three-dimensional electromagnetic structure simulator and applied to build a W-band low noise amplifier module. The measurement of the back-to-back connected waveguide-to-microstrip transition including the empty spaces for the ICs and bias circuits showed the insertion loss less than 3.5 dB and return loss higher than 13.3 dB across the entire W-band without any in-band resonances. The measured insertion loss includes the losses of 8.7 mm-long microstrip line and 41.8 mm-long waveguide section. The designed waveguide package was utilized to build the low noise amplifier module that had a measured gain greater than 14.9 dB from 75 GHz to 105 GHz (>12.9 dB at the entire W-band) and noise figure less than 4.4 dB from 93.5 GHz to 94.5 GHz.

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Ultra compact multi-standard low-noise amplifiers in 28 nm CMOS with inductive peaking

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078717001076 ◽

2017 ◽

Vol 10 (1) ◽

pp. 47-57

Author(s):

Elena Sobotta ◽

Guido Belfiore ◽

Frank Ellinger

Keyword(s):

Noise Figure ◽

Low Noise ◽

Low Noise Amplifiers ◽

Cmos Process ◽

Bandwidth Enhancement ◽

Dc Power ◽

Active Inductors ◽

Inductive Peaking ◽

Noise Amplifier ◽

28 Nm

This work presents the design of two compact multi-standard low-noise amplifier (LNA) in a 28 nm low-power bulk CMOS process. The transistor parameters were optimized by the gm/ID method taking into account the parasitics and the behavior of highly scaled transistors. To cover the industrial science medical (ISM)-bands around 2.4 and 5.8 GHz, the WLAN band as well as the Ku band a bandwidth enhancement is required. Two versions of LNAs, one with vertical inductors and one with active inductors, are implemented and verified by measurements. The noise figure (NF) exhibits 4.2 dB for the LNA with active inductors and 3.5 dB for the LNA with vertical inductors. The voltage gain reaches 12.8 and 13.4 dB, respectively, with a 3 dB-bandwidth of 20 GHz. Both input referred 1-dB-compression points are higher than −12 dBm making the chips attractive for communication standards with high linearity requirements. The chips consume 53 mW DC power and the LNA with active inductors occupies a core area of only 0.0018 mm2, whereas the version with vertical inductors requires 0.021 mm2.

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CMOS low noise amplifiers for 1.575 GHz GPS applications

Advances in Radio Science ◽

10.5194/ars-7-145-2009 ◽

2009 ◽

Vol 7 ◽

pp. 145-150 ◽

Cited By ~ 2

Author(s):

M. Isikhan ◽

A. Richter

Keyword(s):

Noise Figure ◽

Supply Voltage ◽

Low Noise ◽

Performance Criteria ◽

Low Noise Amplifiers ◽

Cmos Process ◽

Quality Factors ◽

Voltage Range ◽

Noise Amplifier ◽

On Chip

Abstract. This paper presents Low Noise Amplifier (LNA) versions designed for 1.575 GHz L1 Band Global Positioning System (GPS) applications. A 0.35 μm standard CMOS process is used for implementation of these design versions. Different versions are designed to compare the results, analyze some effects and optimize some critical performance criteria. On-chip inductors with different quality factors and a slight topology change are utilized to achieve this variety. It is proven through both on-wafer and on-PCB measurements that the LNA versions operate at a supply voltage range varying from 2.1 V to 3.6 V drawing a current of 10 mA and achieve a gain of 13 dB to 17 dB with a Noise Figure (NF) of 1.5 dB. Input referred 1 dB compression point (ICP) is measured as −5.5 dBm and −10 dBm for different versions.

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Design and Development of Monolithic Microwave Integrated Amplifiers and Coupling Circuits for Telecommunication Systems Applications

Active and Passive Electronic Components ◽

10.1080/08827510211275 ◽

2002 ◽

Vol 25 (1) ◽

pp. 1-22 ◽

Cited By ~ 2

Author(s):

R. Makri ◽

M. Gargalakos ◽

N. K. Uzunoglu

Keyword(s):

Fiber Optics ◽

Noise Figure ◽

Input Power ◽

Low Noise ◽

Low Noise Amplifiers ◽

Single Chip ◽

Telecommunication Systems ◽

Noise Amplifier ◽

Shunt Capacitors ◽

Total Gain

Recent advances in printed circuit and packaging technology of microwave and millimeter wave circuits result to the increasing use of MMICs in telecommunication systems. At Microwave and Fiber Optics Lab of NTUA several designs of various MMICs were conducted using the HP Eesof CAD Tool and FET and HEMT models of F20 and H40 GaAs foundry process of GEC Marconi. The designed MMICs are constructed in Europractice Organization while on-wafer probe measurements are performed in the Lab. In that framework, MMIC technologies are employed in the design of power and low noise amplifiers and couplers to be used for mobile and wireless communications as well as remote sensing and radar applications. A medium power linear FET amplifier has been designed with combining techniques on a single chip. The circuit operates at 14.4–15.2 GHz with an input power of−15dB m, a 36 dB total gain, while the input and output VSWR is less than 1.6. Due to high cost of MMIC fabrication only the first subunit was manufactured and tests verified the simulation results. Additionally, novel techniques have been used for the design of two coupling networks at 10 GHz in order to minimize the area occupied. A meander-kind design as well as shunt capacitors were implemented for a90°quadrature coupler and a Wilkinson one in order to reduce size. Finally, a two stages low noise amplifier was designed with the use of H40 GaAs process in order the differences between the relevant designs to be explored. The key specifications for this MMIC LNA include operation at 10 GHz with a total gain of 17 dB while the noise figure is less than 1.5 dB.

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Optimization of spaceflight millimeter-wave impedance matching networks using laser trimming

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078721000180 ◽

2021 ◽

pp. 1-7

Author(s):

K. Parow-Souchon ◽

D. Cuadrado-Calle ◽

S. Rea ◽

M. Henry ◽

M. Merritt ◽

...

Keyword(s):

Integrated Circuits ◽

Millimeter Wave ◽

Impedance Matching ◽

Wave Impedance ◽

Low Noise ◽

Device Performance ◽

Interface Circuits ◽

Interface Circuit ◽

Noise Amplifier

Abstract Realizing packaged state-of-the-art performance of monolithic microwave integrated circuits (MMICs) operating at millimeter wavelengths presents significant challenges in terms of electrical interface circuitry and physical construction. For instance, even with the aid of modern electromagnetic simulation tools, modeling the interaction between the MMIC and its package embedding circuit can lack the necessary precision to achieve optimum device performance. Physical implementation also introduces inaccuracies and requires iterative interface component substitution that can produce variable results, is invasive and risks damaging the MMIC. This paper describes a novel method for in situ optimization of packaged millimeter-wave devices using a pulsed ultraviolet laser to remove pre-selected areas of interface circuit metallization. The method was successfully demonstrated through the optimization of a 183 GHz low noise amplifier destined for use on the MetOp-SG meteorological satellite series. An improvement in amplifier output return loss from an average of 12.9 dB to 22.7 dB was achieved across an operational frequency range of 175–191 GHz and the improved circuit reproduced. We believe that our in situ tuning technique can be applied more widely to planar millimeter-wave interface circuits that are critical in achieving optimum device performance.

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