Smart power IC design methodology based on a new figure of merit (FOM) for standard CMOS technology

In last decades exponential reduction of integrated circuits feature size and increase in operating frequency was achieved in VLSI fabrication industry using the conventional CMOS technology. However the CMOS technology faces serious challenges as the CMOS transistor reaches its physical limits, such as ultra thin gate oxides, short channel effects, doping fluctuations and increased difficulty and consequently increased lithography cost in the nanometer scale. It is projected that the CMOS technology, in its present state will reach its limits when the transistors channel length reaches approximatly 7 nm, probably near 2019. Emerging technologies have been a topic of great interest in the last few years. The emerging technologies in nanoelectronics provide new computing possibilities that arise from their extremely reduced feature sizes. Quantum Cellular Automata (QCA) is one of the most promising emerging technologies in the fast growing area of nanoelectronics. QCA relies mostly on Coulombic interactions and uses innovative processing techniques which are very different from the CMOS-based model. QCAs are not only a new nanoelectronic model but also provide a new method of computation and information process. In QCA circuits computation and data transfer occurs simultaneously. Appling the QCA technology, the elementary building component (QCA cells) cover an area of a few nanometers. For this feature sizes the integration can reach values of 1012 cells/cm2 and the circuit switching frequency the THz level. The implementation of digital logic using QCA nanoelectronic circuits not only drives the already developed systems based on conventional technology to the nanoelectronic era but improves their performance significantly. At the present Ph.D. thesis, a study of QCA circuit clocking schemes is presented showing how these schemes contribute to the robustness of QCA circuits. A novel design of a QCA 2 to 1 multiplexer is presented. The QCA circuit is simulated and its operation is analyzed. A modular design and simulation methodology is developed for the first time. This methodology can be used to design 2n to 1 QCA multiplexers using the 2 to 1 QCA multiplexer as a building block. The design methodology is formulated in order to increase the circuit stability.Furthermore in this Ph.D. thesis, a novel design of a small size, modular quantum-dot cellular automata (QCA) 2n to 1 multiplexer is proposed, These multiplexers can be used for memory addressing. The design objective is to develop an evolving modular design methodology which can produce QCA 2n to 1 multiplexer circuits, improved in terms of circuit area and operating frequency. In these implementations the circuit stability was a major issue and was considered carefully. In the recent years, Cellular Automata (CAs) have been widely used in order to model and simulate physical systems and also to solve scientific problems. CAs have also been successfully used as a VLSI architecture and proved to be very efficient in terms of silicon-area utilization and clock-speed maximization. In the present Ph.D. thesis a design methodology is developed for the first time, which can be used to design CA models using QCA circuitry. The implementation of CAs using QCA nanoelectronic circuits significantly improves their performance due to the unique properties of the nanoelectronic circuits. In this Ph.D. thesis a new CAD system we develope for the first time, and was named Design Automation Tool of 1-D Cellular Automata using Quantum Cellular Automata (DATICAQ), that builds a bridge between one-dimensional CAs as models of physical systems and processes and one-dimensional CAs as a nanoelectronic architecture. The CAD system inputs are the CA dimensionality, size, local rule, and the initial and boundary conditions imposed by the particular problem. DATICAQ produces as output the layout of the QCA implementation of the particular one-dimensional CA model. The proposed system also provides the simulation input vectors and their corresponding outputs, in order to simplify the simulation process. No prior knowledge of QCA circuit designing is required by the user. DATICAQ has been tested for a large number of QCA circuits. Paradigms of QCA circuits implementing CA models for zero and periodic boundary conditions are presented in the thesis. Simulations of CA models and the corresponding QCA circuits showed that the CA rules and models have been successfully implemented. At the present Ph.D. thesis, the design of large scale QCA circuits is analyzed and a study of the problems arising on complex algorithm implementation using QCAs is presented. One of the most important problems of the large scale QCA circuits is the synchronization of the internal signals of the circuit between the subsystems of the large QCA circuit. This problem becomes more difficult when the circuit includes signal loops. In the present thesis a methodology and a QCA circuit is presented for the first time, which solves the above mentioned synchronization problem. The QCA circuit implements the Firing Squad Synchronization Algorithm proposed by Mazoyer in order to solve the synchronization problem. The implementation was obtained using a one-dimensional 3-bit digital CA model. The QCA circuit is simulated and its operation is analyzed.

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ANALYSIS OF FREQUENCY SYNTHESISERS FOR MULTISTANDART WIRELESS TRANSCEIVER / DAŽNIO SINTEZATORIŲ DAUGIASTANDARČIAMS BEVIELIO RYŠIO SIŲSTUVAMS IR IMTUVAMS ANALIZĖ

Mokslas - Lietuvos ateitis ◽

10.3846/mla.2016.931 ◽

2016 ◽

Vol 8 (3) ◽

pp. 302-307 ◽

Cited By ~ 2

Author(s):

Marijan Jurgo ◽

Romualdas Navickas

Keyword(s):

Figure Of Merit ◽

Frequency Synthesizer ◽

Cmos Technology ◽

Wireless Transceivers ◽

Frequency Locking ◽

Wireless Transceiver ◽

Loop Bandwidth ◽

Charge Pump Pll ◽

Chip Size ◽

Better Than

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

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