Low‐jitter spread spectrum clock generator using charge pump frequency detector in 0.18 μm CMOS for USB3.1 transceivers

2017 ◽  
Vol 12 (1) ◽  
pp. 99-107
Author(s):  
Shamin Sadrafshari ◽  
Razieh Eskandari ◽  
Khayrollah Hadidi ◽  
Abdollah Khoei
Keyword(s):  
Spread Spectrum ◽  
Charge Pump ◽  
Clock Generator ◽  
Pump Frequency ◽  
Low Jitter ◽  
Frequency Detector

scholarly journals Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications

2018 ◽  
Vol 8 (6) ◽  
pp. 4120
Author(s):  
Sung Sik Park ◽  
Ju Sang Lee ◽  
Sang Dae Yu
Keyword(s):  
Circuit Simulation ◽  
Pulse Height ◽  
Charge Pump ◽  
Cmos Process ◽  
Charge Pumps ◽  
Current Matching ◽  
Low Jitter ◽  
A New Technique ◽  
Charge Pump Circuit ◽  
Frequency Detector

In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect current-matching characteristics, wide output range, no glitch output current, and no jump output voltage. In order to verify such operation, circuit simulation is performed using 0.18 μm CMOS process parameters.

scholarly journals A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

2015 ◽  
Vol 2015 ◽  
pp. 1-13
Author(s):  
Takashi Kawamoto ◽  
Masato Suzuki ◽  
Takayuki Noto
Keyword(s):  
Spread Spectrum ◽  
Initial Period ◽  
Charge Pump ◽  
Settling Time ◽  
Advanced Technology ◽  
Control Technique ◽  
Signal Frequency ◽  
Clock Generator ◽  
Loop Filter ◽  
Serial Advanced Technology Attachment

A low-jitter fractional spread-spectrum clock generator (SSCG) utilizing a fast-settling dual-charge-pump (CP) technique is developed for serial-advanced technology attachment (SATA) applications. The dual-CP architecture reduces a design area to 60% by shrinking an effective capacitance of a loop filter. Moreover, the settling-time is reduced by 4 μs to charge a current to the capacitor by only main-CP in initial period in settling-time. The SSCG is fabricated in a 0.13 μm CMOS and achieves settling time of 3.91 μs faster than 8.11 μs of a conventional SSCG. The random jitter and total jitter at 250 cycles at 1.5 GHz are less than 3.2 and 10.7 psrms, respectively. The triangular modulation signal frequency is 31.5 kHz and the modulation deviation is from −5000 ppm to 0 ppm at 1.5 GHz. The EMI reduction is 10.0 dB. The design area and power consumption are 300 × 700 μm and 18 mW, respectively.

scholarly journals 2.5 Gbps clock data recovery using 1/4th-rate quadricorrelator frequency detector and skew-calibrated multi-phase clock generator

2006 ◽  
Vol 4 ◽  
pp. 287-291
Author(s):  
S. Tontisirin ◽  
R. Tielert
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Wide Frequency Range ◽  
Data Recovery ◽  
Voltage Controlled Oscillator ◽  
Clock Generator ◽  
Low Jitter ◽  
Phase Clock ◽  
Multi Phase ◽  
Frequency Detector

Abstract. A Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18 μm CMOS technology. It has an active area of 0.7 mm2 and consumes 100 mW at 1.8 V supply. The CDR has low jitter operation in a wide frequency range from 1–2.25 Gb/s. Measurement of Bit-Error Rate is less than 10−12 for 2.25 Gb/s incoming data 27−1 PRBS, jitter peak-to-peak of 0.7 unit interval (UI) modulation at 10 MHz.

Sign in / Sign up

Export Citation Format

Share Document