Distributed charge (sub)micron MOS transistor model

1986 ◽  
Vol 133 (6) ◽  
pp. 207
Author(s):  
J.-J. Charlot ◽  
S. Toutain
2019 ◽  
Vol 66 (1) ◽  
pp. 60-65 ◽  
Author(s):  
Theodor Hillebrand ◽  
Steffen Paul ◽  
Dagmar Peters-Drolshagen

2006 ◽  
pp. 49-95 ◽  
Author(s):  
Matthias Bucher ◽  
Christophe Lallement ◽  
François Krummenacher ◽  
Christian Enz

2020 ◽  
Vol 12 (2) ◽  
pp. 168-172
Author(s):  
Manish Kumar ◽  
Md. Anwar Hussain ◽  
Sajal K. Paul

This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software (version 3.1).


1999 ◽  
Vol 35 (7) ◽  
pp. 561
Author(s):  
Hua-Zhong Yang ◽  
Xia Cai ◽  
Yao-Wei Jia

Author(s):  
S. V. Ryzhov ◽  
◽  
V. V. Andreev ◽  
D. M. Akhmelkin ◽  
M. V. Romanov ◽  
...  

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