Improved performance of 4H-SiC metal-semiconductor field-effect transistors with step p-buffer layer

2011 ◽  
Vol 20 (1) ◽  
pp. 017304 ◽  
Author(s):  
Xiao-Chuan Deng ◽  
Bo Zhang ◽  
You-Run Zhang ◽  
Yi Wang ◽  
Zhao-Ji Li
RSC Advances ◽  
2016 ◽  
Vol 6 (34) ◽  
pp. 28801-28808 ◽  
Author(s):  
Femi Igbari ◽  
Qi-Xun Shang ◽  
Yue-Min Xie ◽  
Xiu-Juan Zhang ◽  
Zhao-Kui Wang ◽  
...  

An approach to achieve improved performance in pentacene-based organic field effect transistors (OFETs) using high-k AlOx prepared by a low temperature sol–gel technique as a thin buffer layer on a SiO2 gate dielectric was demonstrated.


2002 ◽  
Vol 747 ◽  
Author(s):  
K. Nomura ◽  
H. Ohta ◽  
K. Ueda ◽  
T. Kamiya ◽  
M. Hirano ◽  
...  

ABSTRACTTransparent metal-insulator-semiconductor field-effect transistors (MISFETs) were fabricated using a single-crystalline thin film of an n-type transparent oxide semiconductor, a homologous compound InGaO3(ZnO)5, grown by a reactive solid phase epitaxy method. The transparent MISFET exhibited good performances with “normally-off characteristics”, “an on/off current ratio as large as 105” and “insensitivity to visible light”. Field-effect mobility was about 2 cm2(Vs)-1, which is larger than those reported previously for MISFETs fabricated in transparent oxide semiconductors. These improved performance is thought to result from the low defect density and intrinsic-level carrier concentration of the single-crystalline InGaO3(ZnO)5 film.


2007 ◽  
Vol 1029 ◽  
Author(s):  
Shun-Wei Liu ◽  
Jia-Cing Huang ◽  
Chih-Chien Lee ◽  
Chin-Ti Lee ◽  
Juen-Kai Wang

AbstractIn this report, we demonstrate that the performance and stability of pentacene top-contact field-effect transistor can be greatly improved with post-annealing treatment. After post-annealing at 90°C for 12 hours in nitrogen environment, the hole field-effect mobility of 0.3 cm2/Vs and the on/off current ratio of 107 were achieved, demonstrating 100% improvement in performance after the post-annealing treatment. The decay rate of drain current at constant gate and drain-source voltage was found to be decreased by more than 40%. The improved performance is attributed to the elimination of trapped holes and lattice defects in the organic semiconductor layer due to the post-annealing process.


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