A Vertical Polarization-Induced Doping InN/InGaN Heterojunction Tunnel FET with Hetero T-shaped Gate

Chinese Physics B ◽

10.1088/1674-1056/abd73f ◽

2020 ◽

Author(s):

Yuanhao He ◽

Wei Mao ◽

Ming Du ◽

Ziling Peng ◽

Haiyong Wang ◽

...

Keyword(s):

Vertical Polarization ◽

Tunnel Fet

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A simulation Study of Double Channel Trench gate Tunnel FET for Analog Applications

2020 International Conference on Advances in Computing, Communication & Materials (ICACCM) ◽

10.1109/icaccm50413.2020.9212964 ◽

2020 ◽

Author(s):

Tripuresh Joshi ◽

Yashvir Singh ◽

Balraj Singh

Keyword(s):

Simulation Study ◽

Tunnel Fet ◽

Double Channel

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Two-stage amplifier design based on experimental Line-Tunnel FET data

2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s46989.2019.9320637 ◽

2019 ◽

Author(s):

Walter Goncalez Filho ◽

Joao A. Martino ◽

Roberto Rangel ◽

Paula G. D. Agopian ◽

Eddy Simoen ◽

...

Keyword(s):

Two Stage ◽

Tunnel Fet ◽

Experimental Line ◽

Amplifier Design

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Investigation of Homo and Hetero-Junction Double-Gate Tunnel-FET-Based Adiabatic Inverter Circuits

IETE Journal of Research ◽

10.1080/03772063.2020.1859951 ◽

2020 ◽

pp. 1-9

Author(s):

M. Pown ◽

S. Sandeep ◽

B. Lakshmi

Keyword(s):

Double Gate ◽

Tunnel Fet

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Optimization of Electrical Parameters in Dual Dielectric Spacer Overlapped DG Tunnel FET

2020 National Conference on Emerging Trends on Sustainable Technology and Engineering Applications (NCETSTEA) ◽

10.1109/ncetstea48365.2020.9119922 ◽

2020 ◽

Author(s):

Karabi Baruah ◽

Raju Pandey ◽

Ujjal Chakraborty ◽

Srimanta Baishya

Keyword(s):

Electrical Parameters ◽

Tunnel Fet ◽

Dielectric Spacer

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Double gate vertical tunnel FET for hybrid CMOS-TFET based low standby power logic circuits

2013 Annual International Conference on Emerging Research Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy ◽

10.1109/aicera-icmicr.2013.6575992 ◽

2013 ◽

Cited By ~ 5

Author(s):

Abhishek Mishra ◽

Manisha Pattanaik ◽

Varun Sharma

Keyword(s):

Logic Circuits ◽

Double Gate ◽

Tunnel Fet ◽

Hybrid Cmos ◽

Standby Power

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Continuous semianalytical modeling of vertical surrounding-gate tunnel FET: analog/RF performance evaluation

Journal of Computational Electronics ◽

10.1007/s10825-018-1141-9 ◽

2018 ◽

Vol 17 (2) ◽

pp. 724-735 ◽

Cited By ~ 1

Author(s):

Nidhal Abdelmalek ◽

Fayçal Djeffal ◽

Toufik Bentrcia

Keyword(s):

Performance Evaluation ◽

Tunnel Fet ◽

Surrounding Gate ◽

Rf Performance

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Tunnel FET-based ultra-low power, high-sensitivity UHF RFID rectifier

International Symposium on Low Power Electronics and Design (ISLPED) ◽

10.1109/islped.2013.6629287 ◽

2013 ◽

Cited By ~ 22

Author(s):

Huichu Liu ◽

Ramesh Vaddi ◽

Suman Datta ◽

Vijaykrishnan Narayanan

Keyword(s):

Low Power ◽

High Sensitivity ◽

Uhf Rfid ◽

Ultra Low Power ◽

Tunnel Fet

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Tunnel FET technology: A reliability perspective

Microelectronics Reliability ◽

10.1016/j.microrel.2014.02.002 ◽

2014 ◽

Vol 54 (5) ◽

pp. 861-874 ◽

Cited By ~ 79

Author(s):

Suman Datta ◽

Huichu Liu ◽

Vijaykrishnan Narayanan

Keyword(s):

Tunnel Fet

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Planar slot antenna with circular and vertical polarization diversity

Microwave and Optical Technology Letters ◽

10.1002/mop.30765 ◽

2017 ◽

Vol 59 (10) ◽

pp. 2479-2484 ◽

Cited By ~ 2

Author(s):

Nicholas P. Lawrence ◽

Christophe Fumeaux ◽

Derek Abbott

Keyword(s):

Slot Antenna ◽

Polarization Diversity ◽

Vertical Polarization

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Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance

Journal of Semiconductors ◽

10.1088/1674-4926/38/2/024001 ◽

2017 ◽

Vol 38 (2) ◽

pp. 024001 ◽

Cited By ~ 11

Author(s):

Sunny Anand ◽

R. K. Sarin

Keyword(s):

Gate Dielectric ◽

Tunnel Fet ◽

Rf Performance ◽

Dual Material

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