Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

2017 ◽  
Vol 38 (8) ◽  
pp. 085009 ◽  
Author(s):  
Haisong Li ◽  
Longsheng Wu ◽  
Bo Yang ◽  
Yihu Jiang
Keyword(s):  
Pulse Width ◽  
Single Event ◽  
Single Event Transient ◽  
Radiation Hardened

scholarly journals Research on temperature sensitivity of Single-event Transient pulse width in 28-nm bulk technology

2021 ◽  
Vol 2137 (1) ◽  
pp. 012031
Author(s):  
Bohan Zhang ◽  
Bin Liang ◽  
Yahao Fang
Keyword(s):  
Temperature Sensitivity ◽  
Pulse Width ◽  
Single Event ◽  
Single Event Transient ◽  
Worst Case ◽  
Deep Well ◽  
Influence Of Temperature On ◽  
Radiation Resistant ◽  
Bulk Technology ◽  
28 Nm

Abstract The influence of temperature on single-event transient (SET) pulse width has always been a hot issue in the field of anti-irradiation. Based on 3D-TCAD simulation, the temperature sensitivity of the SET pulse width of 28-nm bulk devices has been studied. The simulation results show that the electrical characteristics of the device shows an anti-temperature effect, but the worst case of SET pulse width still occurs at high temperature rather than low temperature. The influence of the triple-well structure on the temperature sensitivity of the SET pulse width has also been studied. The N+ deep well can significantly increase the SET pulse width when hitting NMOS device and enhance the temperature sensitivity of the SET pulse width. The research content of this article will provide reference for the design of radiation resistant chip.

A SEE Hardened Read-Out Circuit of EEPROM for Space Application

2012 ◽  
Vol 198-199 ◽  
pp. 1105-1109
Author(s):  
Xin Jie Zhou ◽  
Jing He Wei ◽  
Lei Lei Li
Keyword(s):  
Circuit Design ◽  
Space Application ◽  
Single Event Upset ◽  
Single Event ◽  
Single Event Transient ◽  
Single Event Effect ◽  
Radiation Hardened

As wide application of EEPROM devices in space and military field, more and more researches focus on its radiation hardened characteristics in international. To improve the single-event effect (SEE) tolerant ability of read-out circuits in the memory, a radiation hardened circuit is designed. The design kernels of radiation hardened latch-flip are given and designed to resist the single-event upset (SEU) effect. A correction circuit is proposed to resist the single-event transient (SET) effect. The performances of this design are: SEU (LET)th ≥ 27 MeV•cm2/mg, SEL(LET)th ≥ 75 MeV•cm2/mg , read out time ≤200 ns. The new design not only satisfied the needs of present work, but supplies a worthful reference for radiation hardened circuit design in future.

scholarly journals Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 27
Author(s):  
Jingtian Liu ◽  
Qian Sun ◽  
Bin Liang ◽  
Jianjun Chen ◽  
Yaqing Chi ◽  
...  
Keyword(s):  
Circuit Design ◽  
Analog Circuits ◽  
Analog Circuit ◽  
Forward Bias ◽  
Cmos Technology ◽  
Common Source ◽  
Single Event ◽  
Single Event Transient ◽  
Body Effect ◽  
Radiation Hardened

In analog circuit design, the bulks of MOSFETs can be tied to their respective sources to remove body effect. This paper models and analyzes the sensitivity of single-event transients (SETs) in common source (CS) amplifier with bulk tied to source (BTS) in 40 nm twin-well bulk CMOS technology. The simulation results present that the proposed BTS radiation-hardened-by-design (RHBD) technique can reduce charge collection and suppress the SET induced perturbation effectively in various input conditions of the circuit. The detailed analysis shows that the mitigation of SET is primarily due to the forward-bias of bulk potential. This technique is universally applicable in radiation-hardening design for analog circuits with negligible penalty.

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