Design of high speed 2-stage OTA for high capacitive load of 120pF and 2.96V

2021 ◽  
Author(s):  
Rohit S Ghatikar ◽  
Nithin M
Keyword(s):  
High Speed ◽  
Slew Rate ◽  
Operational Transconductance Amplifier ◽  
Process Technology ◽  
Charging Time ◽  
Transconductance Amplifier ◽  
Capacitive Load ◽  
Resistive Feedback ◽  
Gain Compensation

Abstract High speed operational transconductance amplifier (OTA) is used to drive high capacitive loads to reduce the charging time while providing adequate gain and stability. A 2-stage amplifier is proposed to provide high slew rate and sufficient gain and stability. 45nm process technology is used to compare performance with differential and telescopic amplifier designs. Resistive feedback and noise-gain compensation techniques are used to drive 120pF load and provide 2.96V at output for a high slew rate of 2.2V/µs.

Low Power Operational Transconductance Amplifier (OTA) with Enhanced DC Gain and Slew-Rate

2013 ◽  
Vol 411-414 ◽  
pp. 1645-1648
Author(s):  
Xiao Zong Huang ◽  
Lun Cai Liu ◽  
Jian Gang Shi ◽  
Wen Gang Huang ◽  
Fan Liu ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Current Mirror ◽  
Slew Rate ◽  
Operational Transconductance Amplifier ◽  
Theory Analysis ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Simulation Results

This paper presents a low-voltage differential operational transconductance amplifier (OTA) with enhanced DC gain and slew-rate. Based on the current mirror OTA topology, the optimization techniques are discussed in this work. The proposed structure achieves enhanced DC gain, unit gain frequency (UGF) and slew-rate (SR) with adding four devices. The design of the OTA is described with theory analysis. The OTA operates at the power supply of 1.8V. Simulation results for 0.18μm standard CMOS technology show that the DC gain increases from 60.6dB to 65dB, the UGF is optimized from 2.5MHz to 4.3MHz, the SR is enhanced from 0.88 V/μs to 4.8 V/μs with close power consumption dramatically.

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology

2011 ◽  
Vol E94-C (3) ◽  
pp. 334-345 ◽  
Author(s):  
Takayuki KONISHI ◽  
Kenji INAZU ◽  
Jun Gyu LEE ◽  
Masanori NATSUI ◽  
Shoichi MASUI ◽  
...  
Keyword(s):  
Low Power ◽  
Design Optimization ◽  
High Speed ◽  
Lookup Table ◽  
Operational Transconductance Amplifier ◽  
Transconductance Amplifier

Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers

2019 ◽  
Vol 15 (4) ◽  
pp. 379-387
Author(s):  
Tayebeh Asiyabi ◽  
Jafar Torfifard
Keyword(s):  
Power Dissipation ◽  
State Of The Art ◽  
Operational Transconductance Amplifier ◽  
Power Efficient ◽  
Miller Compensation ◽  
Transconductance Amplifier ◽  
Multistage Amplifiers ◽  
Dc Gain ◽  
Capacitive Load ◽  
Unity Gain

In this paper, a new architecture of four-stage CMOS operational transconductance amplifier (OTA) based on an alternative differential AC boosting compensation called DACBC is proposed. The presented structure removes feedforward and boosts feedback paths of compensation network simultaneously. Moreover, the presented circuit uses a fairly small compensation capacitor in the order of 1 pF, which makes the circuit very compact regarding enhanced several small-signal and largesignal characteristics. The proposed circuit along with several state-of-the-art schemes from the literature have been extensively analysed and compared together. The simulation results show with the same capacitive load and power dissipation the unity-gain frequency (UGF) can be improved over 60 times than conventional nested Miller compensation. The results of the presented OTA with 15 pF capacitive load demonstrated 65° phase margin, 18.88 MHz as UGF and DC gain of 115 dB with power dissipation of 462 μW from 1.8 V.

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