A Low-Voltage Low-Power Bipolar Transconductor with High-Linearity

2005 ◽  
Vol E88-A (1) ◽  
pp. 384-386 ◽  
Author(s):  
W.-S. CHUNG
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
High Linearity

Low-voltage, low-power, high linearity front-end thermal sensing element

2010 ◽  
Vol 46 (18) ◽  
pp. 1271 ◽  
Author(s):  
P.C. Crepaldi ◽  
R.L. Moreno ◽  
T.C. Pimenta
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Sensing Element ◽  
High Linearity ◽  
Front End ◽  
Thermal Sensing

A Widely Tunable Bandpass CMOS Filter Based on a Low-Voltage Using Operational Transconductance Amplifier Based Active Inductor

2018 ◽  
Vol 7 (3.19) ◽  
pp. 169
Author(s):  
Ridouane Hamdaouy ◽  
Boussetta Mostapha ◽  
Khadija Slaoui
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Active Inductor ◽  
Test Results ◽  
Operational Transconductance Amplifier ◽  
Front Line ◽  
High Linearity ◽  
Transconductance Amplifier

In this paper, an exuberant inductor (ai) with high linearity and high powerful range, together with a base scope of parts, is displayed. This paper offers a compelling method to perceive a cmos band skip channel of low power utilization by method for variety of transconductance in expressions of inclination front line change. The outlined sift through works in a sensibly high recurrence assortment. The reenactment and test results are accommodated 130 nm tsmc13rf rhythm virtuoso.   

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

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